Hi Pavel,
On Tue, 2014-05-27 at 14:40 +0200, ZY - pavel wrote:
Hi!
(Sorry for the delay)
I know u-boot SPL misses critical parts, but I was told that u-boot proper should have everything. Only... I was not able to get it to work. [I'm attempting to load recent u-boot from patched/old u-boot; I know this is not exactly recommended, but due to spl/proper split, it should work AFAIK... and does for old versions.]
I have not tried booting u-boot proper from mainline. It just seemed pointless to me to be working from 2 source trees to make a single product.
I will give it a go though.
Actually the U-Boot is working. You just need to #undef CONFIG_SOCFPGA_VIRTUAL_TARGET and build it. I loaded it using a working Preloader and I can reach the U-Boot console.
Aha, you are right, I forgot about VIRTUAL_TARGET define.
U-Boot 2014.07-rc1-00079-g2072e72-dirty (May 16 2014 - 15:54:55)
CPU : Altera SOCFPGA Platform BOARD : Altera SOCFPGA Cyclone5 Board DRAM: 1 GiB WARNING: Caches not enabled Using default environment
In: serial Out: serial Err: serial Net: No ethernet found.
Do you have any hints how to get ethernet to work?
I yet to upstream the ethernet part yet. I plan to do that once I upstreamed all the minimum SPL code to run on dev kit.
Plus, for me it says:
tertiary u-boot 13.760972 Warning: Your board does not use generic board. Please read tertiary u-boot 13.770775 doc/README.generic-board and take action. Boards not tertiary u-boot 13.779813 upgraded by the late 2014 may break or be removed.
I believe your patch already resolved this :)
As Chin Liang See has said, there are two issues thwarting this: legal AND source conformance. The code we can fix, the legal can only be fixed by bending Altera - I am going to do that too.
We are making some progress on this. Once we have final green light, we will start the upstreaming of SDRAM code. :)
Looking forward :-).
Yup, work in progress. It slightly time consuming especially removing some unused code :)
Thanks Chin Liang
Thanks, Pavel