Re: [U-Boot] [PATCH V2 15/15] imx: add i.MX8MQ EVK support

27 Nov 2018

Hi Stefano,
Do you have any comments on this v2 patchset?
Thanks,
Peng.
...
-----Original Message-----
From: Peng Fan
Sent: 2018年11月20日 18:20
To: sbabic@denx.de; Fabio Estevam fabio.estevam@nxp.com
Cc: u-boot@lists.denx.de; dl-linux-imx linux-imx@nxp.com; Peng Fan
peng.fan@nxp.com
Subject: [PATCH V2 15/15] imx: add i.MX8MQ EVK support
Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy
firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to
DRAM.
The boot log with Arm trusted firmware console enabled:
"
U-Boot SPL 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800)
PMIC:  PFUZE100 ID=0x10
Normal Boot
Trying to boot from MMC2
NOTICE:  Configureing TZASC380
NOTICE:  BL31:
v1.5(release):p9.0.0_1.0.0-beta-20180928-8-ge09c4b62-dirty
NOTICE:  BL31: Built : 09:28:54, Nov  8 2018
lpddr4 swffc start
NOTICE:  sip svc init
U-Boot 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800)
CPU:   Freescale i.MX8MQ rev2.0 at 1000 MHz
Reset cause: POR
Model: Freescale i.MX8MQ EVK
DRAM:  3 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial
Out:   serial
Err:   serial
Net:
Warning: ethernet@30be0000 using MAC address from ROM
eth0: ethernet@30be0000
Hit any key to stop autoboot:  0
"
Signed-off-by: Peng Fan peng.fan@nxp.com
Cc: Fabio Estevam fabio.estevam@nxp.com
Cc: Stefano Babic sbabic@denx.de

V2:
 Rebase to master
 Move ddr phy csr to ddr driver
 reuse lpddr4_defines.h to drop some redundant code.
 CI build: https://travis-ci.org/MrVan/u-boot/builds/457379499
arch/arm/dts/Makefile                         |    2 +
 arch/arm/dts/fsl-imx8mq-evk.dts               |  414 ++++++++
 arch/arm/mach-imx/imx8m/Kconfig               |   13 +
 board/freescale/imx8mq_evk/Kconfig            |   12 +
 board/freescale/imx8mq_evk/MAINTAINERS        |    6 +
 board/freescale/imx8mq_evk/Makefile           |   12 +
 board/freescale/imx8mq_evk/README             |   36 +
 board/freescale/imx8mq_evk/imx8mq_evk.c       |  130 +++
 board/freescale/imx8mq_evk/lpddr4_timing.c    | 1320
+++++++++++++++++++++++++
 board/freescale/imx8mq_evk/lpddr4_timing_b0.c | 1191
++++++++++++++++++++++
 board/freescale/imx8mq_evk/spl.c              |  246 +++++
 configs/imx8mq_evk_defconfig                  |   37 +
 include/configs/imx8mq_evk.h                  |  252 +++++
 13 files changed, 3671 insertions(+)
 create mode 100644 arch/arm/dts/fsl-imx8mq-evk.dts
 create mode 100644 board/freescale/imx8mq_evk/Kconfig
 create mode 100644 board/freescale/imx8mq_evk/MAINTAINERS
 create mode 100644 board/freescale/imx8mq_evk/Makefile
 create mode 100644 board/freescale/imx8mq_evk/README
 create mode 100644 board/freescale/imx8mq_evk/imx8mq_evk.c
 create mode 100644 board/freescale/imx8mq_evk/lpddr4_timing.c
 create mode 100644 board/freescale/imx8mq_evk/lpddr4_timing_b0.c
 create mode 100644 board/freescale/imx8mq_evk/spl.c
 create mode 100644 configs/imx8mq_evk_defconfig
 create mode 100644 include/configs/imx8mq_evk.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1cbb45d679..2be31397d4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -459,6 +459,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
+dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb



dtb-$(CONFIG_RCAR_GEN3) += \
   r8a7795-h3ulcb-u-boot.dtb \
   r8a7795-salvator-x-u-boot.dtb \
diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts
b/arch/arm/dts/fsl-imx8mq-evk.dts
new file mode 100644
index 0000000000..4a08099b3c
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8mq-evk.dts
@@ -0,0 +1,414 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*


Copyright 2018 NXP


*/


+/dts-v1/;



+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x40000000 0x00020000;



+#include "fsl-imx8mq.dtsi"



+/ {

model = "Freescale i.MX8MQ EVK";
compatible = "fsl,imx8mq-evk", "fsl,imx8mq";

chosen {
bootargs = "console=ttymxc0,115200



earlycon=ec_imx6q,0x30860000,115200";

};

regulators {
compatible = "simple-bus";


#address-cells = <1>;


#size-cells = <0>;



reg_usdhc2_vmmc: usdhc2_vmmc {


	compatible = "regulator-fixed";


	regulator-name = "VSD_3V3";


	regulator-min-microvolt = <3300000>;


	regulator-max-microvolt = <3300000>;


	gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;


	enable-active-high;


};


};

pwmleds {
compatible = "pwm-leds";



ledpwm2 {


	label = "PWM2";


	pwms = <&pwm2 0 50000>;


	max-brightness = <255>;


};


};

+};



+&iomuxc {

pinctrl-names = "default";

imx8mq-evk {
pinctrl_fec1: fec1grp {


	fsl,pins = <


		MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3


		MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23


		MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f


		MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f


		MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f


		MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f


		MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91


		MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91


		MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91


		MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91


		MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f


		MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91


		MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL

0x91
		MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL

0x1f
		MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19


	>;


};



pinctrl_i2c1: i2c1grp {


	fsl,pins = <


		MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL	0x4000007f


		MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA	0x4000007f


	>;


};



pinctrl_i2c2: i2c2grp {


	fsl,pins = <


		MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL	0x4000007f


		MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA	0x4000007f


	>;


};



pinctrl_pwm2: pwm2grp {


	fsl,pins = <


		MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT	0x16


	>;


};



pinctrl_qspi: qspigrp {


	fsl,pins = <


		MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82


		MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82


		MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82


		MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82


		MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82


		MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82



	>;


};



pinctrl_usdhc1: usdhc1grp {


	fsl,pins = <


		MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x83


		MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc3


		MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc3


		MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc3


		MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc3


		MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc3


		MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc3


		MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc3


		MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc3


		MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc3


		MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x83


		MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B

0xc1
	>;


};



pinctrl_usdhc1_100mhz: usdhc1grp100mhz {


	fsl,pins = <


		MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x85


		MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc5


		MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc5


		MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc5


		MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc5


		MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc5


		MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc5


		MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc5


		MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc5


		MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc5


		MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x85


		MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B

0xc1
	>;


};



pinctrl_usdhc1_200mhz: usdhc1grp200mhz {


	fsl,pins = <


		MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x87


		MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc7


		MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc7


		MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc7


		MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc7


		MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc7


		MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc7


		MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc7


		MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc7


		MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc7


		MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x87


		MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B

0xc1
	>;


};



pinctrl_usdhc2_gpio: usdhc2grpgpio {


	fsl,pins = <


		MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41


		MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41


	>;


};



pinctrl_usdhc2: usdhc2grp {


	fsl,pins = <


		MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83


		MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3


		MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc3


		MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc3


		MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc3


		MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc3


		MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1


	>;


};



pinctrl_usdhc2_100mhz: usdhc2grp100mhz {


	fsl,pins = <


		MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x85


		MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc5


		MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc5


		MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc5


		MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc5


		MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc5


		MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1


	>;


};



pinctrl_usdhc2_200mhz: usdhc2grp200mhz {


	fsl,pins = <


		MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x87


		MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc7


		MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc7


		MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc7


		MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc7


		MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc7


		MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1


	>;


};



pinctrl_sai2: sai2grp {


	fsl,pins = <


		MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6


		MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6


		MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6


		MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6


		MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0xd6


	>;


};



pinctrl_wdog: wdoggrp {


	fsl,pins = <


		MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6


	>;


};


};

+};



+&fec1 {

pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";

mdio {
#address-cells = <1>;


#size-cells = <0>;



ethphy0: ethernet-phy@0 {


	compatible = "ethernet-phy-ieee802.3-c22";


	reg = <0>;


	at803x,led-act-blind-workaround;


	at803x,eee-disabled;


};


};

+};



+&i2c1 {

clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";

pmic: pfuze100@08 {
compatible = "fsl,pfuze100";


reg = <0x08>;



regulators {


	sw1a_reg: sw1ab {


		regulator-min-microvolt = <300000>;


		regulator-max-microvolt = <1875000>;


		regulator-always-on;


	};



	sw1c_reg: sw1c {


		regulator-min-microvolt = <300000>;


		regulator-max-microvolt = <1875000>;


		regulator-always-on;


	};



	sw2_reg: sw2 {


		regulator-min-microvolt = <800000>;


		regulator-max-microvolt = <3300000>;


		regulator-always-on;


	};



	sw3a_reg: sw3ab {


		regulator-min-microvolt = <400000>;


		regulator-max-microvolt = <1975000>;


		regulator-always-on;


	};



	sw4_reg: sw4 {


		regulator-min-microvolt = <800000>;


		regulator-max-microvolt = <3300000>;


		regulator-always-on;


	};



	swbst_reg: swbst {


		regulator-min-microvolt = <5000000>;


		regulator-max-microvolt = <5150000>;


	};



	snvs_reg: vsnvs {


		regulator-min-microvolt = <1000000>;


		regulator-max-microvolt = <3000000>;


		regulator-always-on;


	};



	vref_reg: vrefddr {


		regulator-always-on;


	};



	vgen1_reg: vgen1 {


		regulator-min-microvolt = <800000>;


		regulator-max-microvolt = <1550000>;


	};



	vgen2_reg: vgen2 {


		regulator-min-microvolt = <800000>;


		regulator-max-microvolt = <1550000>;


		regulator-always-on;


	};



	vgen3_reg: vgen3 {


		regulator-min-microvolt = <1800000>;


		regulator-max-microvolt = <3300000>;


		regulator-always-on;


	};



	vgen4_reg: vgen4 {


		regulator-min-microvolt = <1800000>;


		regulator-max-microvolt = <3300000>;


		regulator-always-on;


	};



	vgen5_reg: vgen5 {


		regulator-min-microvolt = <1800000>;


		regulator-max-microvolt = <3300000>;


		regulator-always-on;


	};



	vgen6_reg: vgen6 {


		regulator-min-microvolt = <1800000>;


		regulator-max-microvolt = <3300000>;


	};


};


};

+};



+&i2c2 {

clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "disabled";

+};



+&pwm2 {

pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";

+};



+&lcdif {

status = "okay";
disp-dev = "mipi_dsi_northwest";
display = <&display0>;

display0: display@0 {
bits-per-pixel = <24>;


bus-width = <24>;



display-timings {


	native-mode = <&timing0>;


	timing0: timing0 {


	clock-frequency = <9200000>;


	hactive = <480>;


	vactive = <272>;


	hfront-porch = <8>;


	hback-porch = <4>;


	hsync-len = <41>;


	vback-porch = <2>;


	vfront-porch = <4>;


	vsync-len = <10>;



	hsync-active = <0>;


	vsync-active = <0>;


	de-active = <1>;


	pixelclk-active = <0>;


	};


};


};

+};



+&qspi {

pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";

flash0: n25q256a@0 {
reg = <0>;


#address-cells = <1>;


#size-cells = <1>;


compatible = "micron,n25q256a";


spi-max-frequency = <29000000>;


spi-nor,ddr-quad-read-dummy = <6>;


};

+};



+&usdhc1 {

pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";

+};



+&usdhc2 {

pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";

+};



+&wdog1 {

pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";

+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig
b/arch/arm/mach-imx/imx8m/Kconfig
index 98d79c3179..317dee9bc1 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -7,4 +7,17 @@ config IMX8M
 config SYS_SOC
   default "imx8m"
+choice

prompt  "NXP i.MX8M board select"
optional


+config TARGET_IMX8MQ_EVK

bool "imx8mq_evk"
select IMX8M
select IMX8M_LPDDR4


+endchoice



+source "board/freescale/imx8mq_evk/Kconfig"



endif
diff --git a/board/freescale/imx8mq_evk/Kconfig
b/board/freescale/imx8mq_evk/Kconfig
new file mode 100644
index 0000000000..421b081c76
--- /dev/null
+++ b/board/freescale/imx8mq_evk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX8MQ_EVK



+config SYS_BOARD

default "imx8mq_evk"


+config SYS_VENDOR

default "freescale"


+config SYS_CONFIG_NAME

default "imx8mq_evk"


+endif
diff --git a/board/freescale/imx8mq_evk/MAINTAINERS
b/board/freescale/imx8mq_evk/MAINTAINERS
new file mode 100644
index 0000000000..a2e320cb10
--- /dev/null
+++ b/board/freescale/imx8mq_evk/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8MQ EVK BOARD
+M:	Peng Fan peng.fan@nxp.com
+S:	Maintained
+F:	board/freescale/imx8mq_evk/
+F:	include/configs/imx8mq_evk.h
+F:	configs/imx8mq_evk_defconfig
diff --git a/board/freescale/imx8mq_evk/Makefile
b/board/freescale/imx8mq_evk/Makefile
new file mode 100644
index 0000000000..cf046963d2
--- /dev/null
+++ b/board/freescale/imx8mq_evk/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#



+obj-y += imx8mq_evk.o



+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o
+endif
diff --git a/board/freescale/imx8mq_evk/README
b/board/freescale/imx8mq_evk/README
new file mode 100644
index 0000000000..07dbfb01fe
--- /dev/null
+++ b/board/freescale/imx8mq_evk/README
@@ -0,0 +1,36 @@
+U-Boot for the NXP i.MX8MQ EVK board



+Quick Start
+====================
+- Build the ARM Trusted firmware binary
+- Get ddr and hdmi fimware
+- Build U-Boot
+- Boot



+Get and Build the ARM Trusted firmware
+====================
+Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
+branch: imx_4.14.62_1.0.0_beta
+$ make PLAT=imx8mq bl31



+Get the ddr and hdmi firmware
+====================
+Note: srctree is U-Boot source directory
+$ wget
https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
+$ chmod +x firmware-imx-7.9.bin
+$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin
$(srctree)
+$ cp
firmware-imx-7.9/firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin
$(srctee)



+Build U-Boot
+====================
+$ export ARCH=arm64
+$ export CROSS_COMPILE=aarch64-poky-linux-
+$ make imx8mq_evk_defconfig
+$ make flash.bin



+Burn the flash.bin to MicroSD card offset 33KB
+$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33



+Boot
+====================
+Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c
b/board/freescale/imx8mq_evk/imx8mq_evk.c
new file mode 100644
index 0000000000..54e0c38431
--- /dev/null
+++ b/board/freescale/imx8mq_evk/imx8mq_evk.c
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*


Copyright 2018 NXP


*/


+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"



+DECLARE_GLOBAL_DATA_PTR;



+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)



+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS |
PAD_CTL_PUE)



+static iomux_v3_cfg_t const wdog_pads[] = {

IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B |

MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};



+static iomux_v3_cfg_t const uart_pads[] = {

IMX8MQ_PAD_UART1_RXD__UART1_RX |

MUX_PAD_CTRL(UART_PAD_CTRL),

IMX8MQ_PAD_UART1_TXD__UART1_TX |

MUX_PAD_CTRL(UART_PAD_CTRL),
+};



+int board_early_init_f(void)
+{

struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;

imx_iomux_v3_setup_multiple_pads(wdog_pads,

ARRAY_SIZE(wdog_pads));

set_wdog_reset(wdog);

imx_iomux_v3_setup_multiple_pads(uart_pads,

ARRAY_SIZE(uart_pads));


return 0;

+}



+int dram_init(void)
+{

/* rom_pointer[1] contains the size of TEE occupies */
if (rom_pointer[1])
gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];


else
gd->ram_size = PHYS_SDRAM_SIZE;



return 0;

+}



+#ifdef CONFIG_FEC_MXC
+#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
+static iomux_v3_cfg_t const fec1_rst_pads[] = {

IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 |

MUX_PAD_CTRL(NO_PAD_CTRL),
+};



+static void setup_iomux_fec(void)
+{

imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
			 ARRAY_SIZE(fec1_rst_pads));



gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
udelay(500);
gpio_direction_output(IMX_GPIO_NR(1, 9), 1);

+}



+static int setup_fec(void)
+{

struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;



setup_iomux_fec();

/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
return set_clk_enet(ENET_125MHZ);

+}



+int board_phy_config(struct phy_device *phydev)
+{

/* enable rgmii rxc skew and phy mode select to RGMII copper */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);

phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);

if (phydev->drv->config)
phydev->drv->config(phydev);


return 0;

+}
+#endif



+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC

setup_fec();

+#endif


return 0;

+}



+int board_mmc_get_env_dev(int devno)
+{

return devno;

+}



+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

env_set("board_name", "EVK");
env_set("board_rev", "iMX8MQ");

+#endif


return 0;

+}
diff --git a/board/freescale/imx8mq_evk/lpddr4_timing.c
b/board/freescale/imx8mq_evk/lpddr4_timing.c
new file mode 100644
index 0000000000..f7ea799343
--- /dev/null
+++ b/board/freescale/imx8mq_evk/lpddr4_timing.c
@@ -0,0 +1,1320 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*


Copyright 2018 NXP


*/


+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>



+#define WR_POST_EXT_3200	/* recommened to define */



+struct dram_cfg_param lpddr4_ddrc_cfg[] = {

/* Start to config, default 3200mbps */
{ DDRC_DBG1(0), 0x00000001 },
{ DDRC_PWRCTL(0), 0x00000001 },
{ DDRC_MSTR(0), 0xa3080020 },
{ DDRC_MSTR2(0), 0x00000000 },
{ DDRC_RFSHTMG(0), 0x006100E0 },
{ DDRC_INIT0(0), 0xC003061B },
{ DDRC_INIT1(0), 0x009D0000 },
{ DDRC_INIT3(0), 0x00D4002D },

+#ifdef WR_POST_EXT_3200

{ DDRC_INIT4(0), 0x00330008 },

+#else

{ DDRC_INIT4(0), 0x00310008 },

+#endif

{ DDRC_INIT6(0), 0x0066004a },
{ DDRC_INIT7(0), 0x0006004a },

{ DDRC_DRAMTMG0(0), 0x1A201B22 },
{ DDRC_DRAMTMG1(0), 0x00060633 },
{ DDRC_DRAMTMG3(0), 0x00C0C000 },
{ DDRC_DRAMTMG4(0), 0x0F04080F },
{ DDRC_DRAMTMG5(0), 0x02040C0C },
{ DDRC_DRAMTMG6(0), 0x01010007 },
{ DDRC_DRAMTMG7(0), 0x00000401 },
{ DDRC_DRAMTMG12(0), 0x00020600 },
{ DDRC_DRAMTMG13(0), 0x0C100002 },
{ DDRC_DRAMTMG14(0), 0x000000E6 },
{ DDRC_DRAMTMG17(0), 0x00A00050 },

{ DDRC_ZQCTL0(0), 0x03200018 },
{ DDRC_ZQCTL1(0), 0x028061A8 },
{ DDRC_ZQCTL2(0), 0x00000000 },

{ DDRC_DFITMG0(0), 0x0497820A },
{ DDRC_DFITMG1(0), 0x00080303 },
{ DDRC_DFIUPD0(0), 0xE0400018 },
{ DDRC_DFIUPD1(0), 0x00DF00E4 },
{ DDRC_DFIUPD2(0), 0x80000000 },
{ DDRC_DFIMISC(0), 0x00000011 },
{ DDRC_DFITMG2(0), 0x0000170A },

{ DDRC_DBICTL(0), 0x00000001 },
{ DDRC_DFIPHYMSTR(0), 0x00000001 },
{ DDRC_RANKCTL(0), 0x00000c99 },
{ DDRC_DRAMTMG2(0), 0x070E171a },

/* address mapping */
{ DDRC_ADDRMAP0(0), 0x00000015 },
{ DDRC_ADDRMAP3(0), 0x00000000 },
{ DDRC_ADDRMAP4(0), 0x00001F1F },
/* bank interleave */
{ DDRC_ADDRMAP1(0), 0x00080808 },
{ DDRC_ADDRMAP5(0), 0x07070707 },
{ DDRC_ADDRMAP6(0), 0x08080707 },

/* performance setting */
{ DDRC_ODTCFG(0), 0x0b060908 },
{ DDRC_ODTMAP(0), 0x00000000 },
{ DDRC_SCHED(0), 0x29511505 },
{ DDRC_SCHED1(0), 0x0000002c },
{ DDRC_PERFHPR1(0), 0x5900575b },
{ DDRC_PERFLPR1(0), 0x00000009 },
{ DDRC_PERFWR1(0), 0x02005574 },
{ DDRC_DBG0(0), 0x00000016 },
{ DDRC_DBG1(0), 0x00000000 },
{ DDRC_DBGCMD(0), 0x00000000 },
{ DDRC_SWCTL(0), 0x00000001 },
{ DDRC_POISONCFG(0), 0x00000011 },
{ DDRC_PCCFG(0), 0x00000111 },
{ DDRC_PCFGR_0(0), 0x000010f3 },
{ DDRC_PCFGW_0(0), 0x000072ff },
{ DDRC_PCTRL_0(0), 0x00000001 },
{ DDRC_PCFGQOS0_0(0), 0x01110d00 },
{ DDRC_PCFGQOS1_0(0), 0x00620790 },
{ DDRC_PCFGWQOS0_0(0), 0x00100001 },
{ DDRC_PCFGWQOS1_0(0), 0x0000041f },

/* Frequency 1: 400mbps */
{ DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
{ DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
{ DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
{ DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
{ DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
{ DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
{ DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
{ DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
{ DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
{ DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
{ DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
{ DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
{ DDRC_FREQ1_DFITMG0(0), 0x03818200 },
{ DDRC_FREQ1_DFITMG2(0), 0x00000000 },
{ DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
{ DDRC_FREQ1_INIT3(0), 0x00840000 },
{ DDRC_FREQ1_INIT4(0), 0x00310008 },
{ DDRC_FREQ1_INIT6(0), 0x0066004a },
{ DDRC_FREQ1_INIT7(0), 0x0006004a },

/* Frequency 2: 100mbps */
{ DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
{ DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
{ DDRC_FREQ2_DRAMTMG2(0), 0x0305090c },
{ DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
{ DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
{ DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
{ DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
{ DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
{ DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
{ DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
{ DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
{ DDRC_FREQ2_DFITMG0(0), 0x03818200 },
{ DDRC_FREQ2_DFITMG2(0), 0x00000000 },
{ DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
{ DDRC_FREQ2_INIT3(0), 0x00840000 },
{ DDRC_FREQ2_INIT4(0), 0x00310008 },
{ DDRC_FREQ2_INIT6(0), 0x0066004a },
{ DDRC_FREQ2_INIT7(0), 0x0006004a },

+};



+/* PHY Initialize Configuration */
+struct dram_cfg_param lpddr4_ddrphy_cfg[] = {

{ 0x20110, 0x02 },
{ 0x20111, 0x03 },
{ 0x20112, 0x04 },
{ 0x20113, 0x05 },
{ 0x20114, 0x00 },
{ 0x20115, 0x01 },

{ 0x1005f, 0x1ff },
{ 0x1015f, 0x1ff },
{ 0x1105f, 0x1ff },
{ 0x1115f, 0x1ff },
{ 0x1205f, 0x1ff },
{ 0x1215f, 0x1ff },
{ 0x1305f, 0x1ff },
{ 0x1315f, 0x1ff },

{ 0x11005f, 0x1ff },
{ 0x11015f, 0x1ff },
{ 0x11105f, 0x1ff },
{ 0x11115f, 0x1ff },
{ 0x11205f, 0x1ff },
{ 0x11215f, 0x1ff },
{ 0x11305f, 0x1ff },
{ 0x11315f, 0x1ff },

{ 0x21005f, 0x1ff },
{ 0x21015f, 0x1ff },
{ 0x21105f, 0x1ff },
{ 0x21115f, 0x1ff },
{ 0x21205f, 0x1ff },
{ 0x21215f, 0x1ff },
{ 0x21305f, 0x1ff },
{ 0x21315f, 0x1ff },

{ 0x55, 0x1ff },
{ 0x1055, 0x1ff },
{ 0x2055, 0x1ff },
{ 0x3055, 0x1ff },
{ 0x4055, 0x1ff },
{ 0x5055, 0x1ff },
{ 0x6055, 0x1ff },
{ 0x7055, 0x1ff },
{ 0x8055, 0x1ff },
{ 0x9055, 0x1ff },

{ 0x200c5, 0x19 },
{ 0x1200c5, 0x7 },
{ 0x2200c5, 0x7 },

{ 0x2002e, 0x2 },
{ 0x12002e, 0x2 },
{ 0x22002e, 0x2 },

{ 0x90204, 0x0 },
{ 0x190204, 0x0 },
{ 0x290204, 0x0 },


+#ifdef WR_POST_EXT_3200

{ 0x20024, 0xeb },

+#else

{ 0x20024, 0xab },

+#endif

{ 0x2003a, 0x0 },
{ 0x120024, 0xab },
{ 0x2003a, 0x0 },
{ 0x220024, 0xab },
{ 0x2003a, 0x0 },
{ 0x20056, 0x3 },
{ 0x120056, 0xa },
{ 0x220056, 0xa },
{ 0x1004d, 0xe00 },
{ 0x1014d, 0xe00 },
{ 0x1104d, 0xe00 },
{ 0x1114d, 0xe00 },
{ 0x1204d, 0xe00 },
{ 0x1214d, 0xe00 },
{ 0x1304d, 0xe00 },
{ 0x1314d, 0xe00 },
{ 0x11004d, 0xe00 },
{ 0x11014d, 0xe00 },
{ 0x11104d, 0xe00 },
{ 0x11114d, 0xe00 },
{ 0x11204d, 0xe00 },
{ 0x11214d, 0xe00 },
{ 0x11304d, 0xe00 },
{ 0x11314d, 0xe00 },
{ 0x21004d, 0xe00 },
{ 0x21014d, 0xe00 },
{ 0x21104d, 0xe00 },
{ 0x21114d, 0xe00 },
{ 0x21204d, 0xe00 },
{ 0x21214d, 0xe00 },
{ 0x21304d, 0xe00 },
{ 0x21314d, 0xe00 },

{ 0x10049, 0xfbe },
{ 0x10149, 0xfbe },
{ 0x11049, 0xfbe },
{ 0x11149, 0xfbe },
{ 0x12049, 0xfbe },
{ 0x12149, 0xfbe },
{ 0x13049, 0xfbe },
{ 0x13149, 0xfbe },
{ 0x110049, 0xfbe },
{ 0x110149, 0xfbe },
{ 0x111049, 0xfbe },
{ 0x111149, 0xfbe },
{ 0x112049, 0xfbe },
{ 0x112149, 0xfbe },
{ 0x113049, 0xfbe },
{ 0x113149, 0xfbe },
{ 0x210049, 0xfbe },
{ 0x210149, 0xfbe },
{ 0x211049, 0xfbe },
{ 0x211149, 0xfbe },
{ 0x212049, 0xfbe },
{ 0x212149, 0xfbe },
{ 0x213049, 0xfbe },
{ 0x213149, 0xfbe },

{ 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
{ 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) |

LPDDR4_PHY_ADDR_RON) },

{ 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) |

LPDDR4_PHY_ADDR_RON) },

{ 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) |

LPDDR4_PHY_ADDR_RON) },

{ 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) |

LPDDR4_PHY_ADDR_RON) },

{ 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) |

LPDDR4_PHY_ADDR_RON) },

{ 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) |

LPDDR4_PHY_ADDR_RON) },

{ 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) |

LPDDR4_PHY_ADDR_RON) },

{ 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) |

LPDDR4_PHY_ADDR_RON) },

{ 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) |

LPDDR4_PHY_ADDR_RON) },


{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
{ 0x20008, 0x320 },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
{ 0x200b2, 0x104 },
{ 0x10043, 0x5a1 },
{ 0x10143, 0x5a1 },
{ 0x11043, 0x5a1 },
{ 0x11143, 0x5a1 },
{ 0x12043, 0x5a1 },
{ 0x12143, 0x5a1 },
{ 0x13043, 0x5a1 },
{ 0x13143, 0x5a1 },
{ 0x1200b2, 0x104 },
{ 0x110043, 0x5a1 },
{ 0x110143, 0x5a1 },
{ 0x111043, 0x5a1 },
{ 0x111143, 0x5a1 },
{ 0x112043, 0x5a1 },
{ 0x112143, 0x5a1 },
{ 0x113043, 0x5a1 },
{ 0x113143, 0x5a1 },
{ 0x2200b2, 0x104 },
{ 0x210043, 0x5a1 },
{ 0x210143, 0x5a1 },
{ 0x211043, 0x5a1 },
{ 0x211143, 0x5a1 },
{ 0x212043, 0x5a1 },
{ 0x212143, 0x5a1 },
{ 0x213043, 0x5a1 },
{ 0x213143, 0x5a1 },
{ 0x200fa, 0x1 },
{ 0x1200fa, 0x1 },
{ 0x2200fa, 0x1 },
{ 0x20019, 0x1 },
{ 0x120019, 0x1 },
{ 0x220019, 0x1 },
{ 0x200f0, 0x660 },
{ 0x200f1, 0x0 },
{ 0x200f2, 0x4444 },
{ 0x200f3, 0x8888 },
{ 0x200f4, 0x5665 },
{ 0x200f5, 0x0 },
{ 0x200f6, 0x0 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
{ 0x2002d, 0x0 },
{ 0x12002d, 0x0 },
{ 0x22002d, 0x0 },

{ 0x200c7, 0x80 },
{ 0x1200c7, 0x80 },
{ 0x2200c7, 0x80 },
{ 0x200ca, 0x106 },
{ 0x1200ca, 0x106 },
{ 0x2200ca, 0x106 },

+};



+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_cfg[] = {

{ 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
{ 0x54002, 0x0 },
{ 0x54003, 0xc80 },
{ 0x54004, 0x2 },
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY

Ron/Rtt */

{ 0x54006, LPDDR4_PHY_VREF_VALUE },
{ 0x54007, 0x0 },
{ 0x54008, 0x131f },
{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
{ 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
{ 0x5400c, 0x0 },
{ 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
{ 0x5400e, 0x0 },
{ 0x5400f, 0x0 },
{ 0x54010, 0x0 },
{ 0x54011, 0x0 },
{ 0x54012, 0x310 },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
{ 0x54016, 0x0 },
{ 0x54017, 0x0 },
{ 0x54018, 0x0 },

{ 0x54019, 0x2dd4 },

+#ifdef WR_POST_EXT_3200

{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },

+#else

{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },

+#endif

{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },


{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
{ 0x5401d, 0x0 },
{ 0x5401e, LPDDR4_MR22_RANK0 },
{ 0x5401f, 0x2dd4 },

+#ifdef WR_POST_EXT_3200

{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },

+#else

{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },

+#endif

{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },


{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
{ 0x54023, 0x0 },
{ 0x54024, LPDDR4_MR22_RANK1 },

{ 0x54025, 0x0 },
{ 0x54026, 0x0 },
{ 0x54027, 0x0 },
{ 0x54028, 0x0 },
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
{ 0x54030, 0x0 },
{ 0x54031, 0x0 },
{ 0x54032, 0xd400 },
/* MR3/MR2 */

+#ifdef WR_POST_EXT_3200

{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ },

+#else

{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },

+#endif

/* MR11/MR4 */
{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
/* self:0x284d//MR13/MR12 */
{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
/* MR16/MR14*/
{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ },
{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ },
/* MR1 */
{ 0x54038, 0xd400 },
/* MR3/MR2 */

+#ifdef WR_POST_EXT_3200

{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ },

+#else

{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },

+#endif

/* MR11/MR4 */
{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
/* self:0x284d//MR13/MR12 */
{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
/* MR16/MR14 */
{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
/* { 0x5403d, 0x500 } */
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
{ 0x5403e, 0x0 },
{ 0x5403f, 0x0 },
{ 0x54040, 0x0 },
{ 0x54041, 0x0 },
{ 0x54042, 0x0 },
{ 0x54043, 0x0 },
{ 0x54044, 0x0 },
{ 0xd0000, 0x1 },

+};



+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp1_cfg[] = {

{ 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
{ 0x54002, 0x101 },
{ 0x54003, 0x190 },
{ 0x54004, 0x2 },
/* PHY Ron/Rtt */
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ },
{ 0x54006, LPDDR4_PHY_VREF_VALUE },
{ 0x54007, 0x0 },
{ 0x54008, LPDDR4_TRAIN_SEQ_400 },
{ 0x54009, LPDDR4_HDT_CTL_400_1D },
{ 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
{ 0x5400c, 0x0 },
{ 0x5400d, (LPDDR4_CATRAIN_400 << 8) },
{ 0x5400e, 0x0 },
{ 0x5400f, 0x0 },
{ 0x54010, 0x0 },
{ 0x54011, 0x0 },
{ 0x54012, 0x310 },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
{ 0x54016, 0x0 },
{ 0x54017, 0x0 },
{ 0x54018, 0x0 },
{ 0x54019, 0x84 },
/* MR4/MR3 */
{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ },
/* MR12/MR11 */
{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
    LPDDR4_RTT_DQ)/*0x4d46*/ },


/* self:0x4d28//MR14/MR13 */
{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) |

0x08)/*0x4d08*/ },

{ 0x5401d, 0x0 },
{ 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ },
{ 0x5401f, 0x84 },
{ 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */
{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
    LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */


/* self:0x4d28//MR14/MR13 */
{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) |

0x08)/*0x4d08*/ },

{ 0x54023, 0x0 },
{ 0x54024, LPDDR4_MR22_RANK1 },
{ 0x54025, 0x0 },
{ 0x54026, 0x0 },
{ 0x54027, 0x0 },
{ 0x54028, 0x0 },
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
{ 0x54030, 0x0 },
{ 0x54031, 0x0 },
{ 0x54032, 0x8400 },
{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
{ 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
{ 0x54038, 0x8400 },
{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
{ 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
{ 0x5403e, 0x0 },
{ 0x5403f, 0x0 },
{ 0x54040, 0x0 },
{ 0x54041, 0x0 },
{ 0x54042, 0x0 },
{ 0x54043, 0x0 },
{ 0x54044, 0x0 },
{ 0xd0000, 0x1 },

+};



+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp2_cfg[] = {

{ 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
{ 0x54002, 0x102 },
{ 0x54003, 0x64 },
{ 0x54004, 0x2 },
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
{ 0x54006, LPDDR4_PHY_VREF_VALUE },
{ 0x54007, 0x0 },
{ 0x54008, LPDDR4_TRAIN_SEQ_100 },
{ 0x54009, LPDDR4_HDT_CTL_100_1D },
{ 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
{ 0x5400c, 0x0 },
{ 0x5400d, (LPDDR4_CATRAIN_100 << 8) },
{ 0x5400e, 0x0 },
{ 0x5400f, 0x0 },
{ 0x54010, 0x0 },
{ 0x54011, 0x0 },
{ 0x54012, 0x310 },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
{ 0x54016, 0x0 },
{ 0x54017, 0x0 },
{ 0x54018, 0x0 },
{ 0x54019, 0x84 },
{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
    LPDDR4_RTT_DQ) },


{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
{ 0x5401d, 0x0 },
{ 0x5401e, LPDDR4_MR22_RANK0 },
{ 0x5401f, 0x84 },
{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
    LPDDR4_RTT_DQ) },


{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
{ 0x54023, 0x0 },
{ 0x54024, LPDDR4_MR22_RANK1 },
{ 0x54025, 0x0 },
{ 0x54026, 0x0 },
{ 0x54027, 0x0 },
{ 0x54028, 0x0 },
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
{ 0x54030, 0x0 },
{ 0x54031, 0x0 },
{ 0x54032, 0x8400 },
{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
{ 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
{ 0x54038, 0x8400 },
{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
{ 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
{ 0x5403e, 0x0 },
{ 0x5403f, 0x0 },
{ 0x54040, 0x0 },
{ 0x54041, 0x0 },
{ 0x54042, 0x0 },
{ 0x54043, 0x0 },
{ 0x54044, 0x0 },
{ 0xd0000, 0x1 },

+};



+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {

{ 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
{ 0x54002, 0x0 },
{ 0x54003, 0xc80 },
{ 0x54004, 0x2 },
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
{ 0x54006, LPDDR4_PHY_VREF_VALUE },
{ 0x54007, 0x0 },
{ 0x54008, 0x61 },
{ 0x54009, LPDDR4_HDT_CTL_2D },
{ 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
{ 0x5400c, 0x0 },
{ 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
{ 0x5400e, 0x0 },
{ 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
{ 0x54010, LPDDR4_2D_WEIGHT },
{ 0x54011, 0x0 },
{ 0x54012, 0x310 },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
{ 0x54016, 0x0 },
{ 0x54017, 0x0 },
{ 0x54018, 0x0 },
{ 0x54019, 0x2dd4 },

+#ifdef WR_POST_EXT_3200

{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },

+#else

{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },

+#endif

{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },


{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
{ 0x5401d, 0x0 },
{ 0x5401e, LPDDR4_MR22_RANK0 },
{ 0x5401f, 0x2dd4 },

+#ifdef WR_POST_EXT_3200

{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },

+#else

{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },

+#endif

{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },


{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
{ 0x54023, 0x0 },
{ 0x54024, LPDDR4_MR22_RANK1 },
{ 0x54025, 0x0 },
{ 0x54026, 0x0 },
{ 0x54027, 0x0 },
{ 0x54028, 0x0 },
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
{ 0x54030, 0x0 },
{ 0x54031, 0x0 },

{ 0x54032, 0xd400 },

+#ifdef WR_POST_EXT_3200

{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },

+#else

{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },

+#endif

{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
{ 0x54038, 0xd400 },

+#ifdef WR_POST_EXT_3200

{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },

+#else

{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },

+#endif

{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
{ 0x5403e, 0x0 },
{ 0x5403f, 0x0 },
{ 0x54040, 0x0 },
{ 0x54041, 0x0 },
{ 0x54042, 0x0 },
{ 0x54043, 0x0 },
{ 0x54044, 0x0 },
{ 0xd0000, 0x1 },

+};



+/* DRAM PHY init engine image */
+struct dram_cfg_param lpddr4_phy_pie[] = {

{ 0xd0000, 0x0 },
{ 0x90000, 0x10 },
{ 0x90001, 0x400 },
{ 0x90002, 0x10e },
{ 0x90003, 0x0 },
{ 0x90004, 0x0 },
{ 0x90005, 0x8 },
{ 0x90029, 0xb },
{ 0x9002a, 0x480 },
{ 0x9002b, 0x109 },
{ 0x9002c, 0x8 },
{ 0x9002d, 0x448 },
{ 0x9002e, 0x139 },
{ 0x9002f, 0x8 },
{ 0x90030, 0x478 },
{ 0x90031, 0x109 },
{ 0x90032, 0x0 },
{ 0x90033, 0xe8 },
{ 0x90034, 0x109 },
{ 0x90035, 0x2 },
{ 0x90036, 0x10 },
{ 0x90037, 0x139 },
{ 0x90038, 0xf },
{ 0x90039, 0x7c0 },
{ 0x9003a, 0x139 },
{ 0x9003b, 0x44 },
{ 0x9003c, 0x630 },
{ 0x9003d, 0x159 },
{ 0x9003e, 0x14f },
{ 0x9003f, 0x630 },
{ 0x90040, 0x159 },
{ 0x90041, 0x47 },
{ 0x90042, 0x630 },
{ 0x90043, 0x149 },
{ 0x90044, 0x4f },
{ 0x90045, 0x630 },
{ 0x90046, 0x179 },
{ 0x90047, 0x8 },
{ 0x90048, 0xe0 },
{ 0x90049, 0x109 },
{ 0x9004a, 0x0 },
{ 0x9004b, 0x7c8 },
{ 0x9004c, 0x109 },
{ 0x9004d, 0x0 },
{ 0x9004e, 0x1 },
{ 0x9004f, 0x8 },
{ 0x90050, 0x0 },
{ 0x90051, 0x45a },
{ 0x90052, 0x9 },
{ 0x90053, 0x0 },
{ 0x90054, 0x448 },
{ 0x90055, 0x109 },
{ 0x90056, 0x40 },
{ 0x90057, 0x630 },
{ 0x90058, 0x179 },
{ 0x90059, 0x1 },
{ 0x9005a, 0x618 },
{ 0x9005b, 0x109 },
{ 0x9005c, 0x40c0 },
{ 0x9005d, 0x630 },
{ 0x9005e, 0x149 },
{ 0x9005f, 0x8 },
{ 0x90060, 0x4 },
{ 0x90061, 0x48 },
{ 0x90062, 0x4040 },
{ 0x90063, 0x630 },
{ 0x90064, 0x149 },
{ 0x90065, 0x0 },
{ 0x90066, 0x4 },
{ 0x90067, 0x48 },
{ 0x90068, 0x40 },
{ 0x90069, 0x630 },
{ 0x9006a, 0x149 },
{ 0x9006b, 0x10 },
{ 0x9006c, 0x4 },
{ 0x9006d, 0x18 },
{ 0x9006e, 0x0 },
{ 0x9006f, 0x4 },
{ 0x90070, 0x78 },
{ 0x90071, 0x549 },
{ 0x90072, 0x630 },
{ 0x90073, 0x159 },
{ 0x90074, 0xd49 },
{ 0x90075, 0x630 },
{ 0x90076, 0x159 },
{ 0x90077, 0x94a },
{ 0x90078, 0x630 },
{ 0x90079, 0x159 },
{ 0x9007a, 0x441 },
{ 0x9007b, 0x630 },
{ 0x9007c, 0x149 },
{ 0x9007d, 0x42 },
{ 0x9007e, 0x630 },
{ 0x9007f, 0x149 },
{ 0x90080, 0x1 },
{ 0x90081, 0x630 },
{ 0x90082, 0x149 },
{ 0x90083, 0x0 },
{ 0x90084, 0xe0 },
{ 0x90085, 0x109 },
{ 0x90086, 0xa },
{ 0x90087, 0x10 },
{ 0x90088, 0x109 },
{ 0x90089, 0x9 },
{ 0x9008a, 0x3c0 },
{ 0x9008b, 0x149 },
{ 0x9008c, 0x9 },
{ 0x9008d, 0x3c0 },
{ 0x9008e, 0x159 },
{ 0x9008f, 0x18 },
{ 0x90090, 0x10 },
{ 0x90091, 0x109 },
{ 0x90092, 0x0 },
{ 0x90093, 0x3c0 },
{ 0x90094, 0x109 },
{ 0x90095, 0x18 },
{ 0x90096, 0x4 },
{ 0x90097, 0x48 },
{ 0x90098, 0x18 },
{ 0x90099, 0x4 },
{ 0x9009a, 0x58 },
{ 0x9009b, 0xa },
{ 0x9009c, 0x10 },
{ 0x9009d, 0x109 },
{ 0x9009e, 0x2 },
{ 0x9009f, 0x10 },
{ 0x900a0, 0x109 },
{ 0x900a1, 0x5 },
{ 0x900a2, 0x7c0 },
{ 0x900a3, 0x109 },
{ 0x900a4, 0x10 },
{ 0x900a5, 0x10 },
{ 0x900a6, 0x109 },
{ 0x40000, 0x811 },
{ 0x40020, 0x880 },
{ 0x40040, 0x0 },
{ 0x40060, 0x0 },
{ 0x40001, 0x4008 },
{ 0x40021, 0x83 },
{ 0x40041, 0x4f },
{ 0x40061, 0x0 },
{ 0x40002, 0x4040 },
{ 0x40022, 0x83 },
{ 0x40042, 0x51 },
{ 0x40062, 0x0 },
{ 0x40003, 0x811 },
{ 0x40023, 0x880 },
{ 0x40043, 0x0 },
{ 0x40063, 0x0 },
{ 0x40004, 0x720 },
{ 0x40024, 0xf },
{ 0x40044, 0x1740 },
{ 0x40064, 0x0 },
{ 0x40005, 0x16 },
{ 0x40025, 0x83 },
{ 0x40045, 0x4b },
{ 0x40065, 0x0 },
{ 0x40006, 0x716 },
{ 0x40026, 0xf },
{ 0x40046, 0x2001 },
{ 0x40066, 0x0 },
{ 0x40007, 0x716 },
{ 0x40027, 0xf },
{ 0x40047, 0x2800 },
{ 0x40067, 0x0 },
{ 0x40008, 0x716 },
{ 0x40028, 0xf },
{ 0x40048, 0xf00 },
{ 0x40068, 0x0 },
{ 0x40009, 0x720 },
{ 0x40029, 0xf },
{ 0x40049, 0x1400 },
{ 0x40069, 0x0 },
{ 0x4000a, 0xe08 },
{ 0x4002a, 0xc15 },
{ 0x4004a, 0x0 },
{ 0x4006a, 0x0 },
{ 0x4000b, 0x623 },
{ 0x4002b, 0x15 },
{ 0x4004b, 0x0 },
{ 0x4006b, 0x0 },
{ 0x4000c, 0x4028 },
{ 0x4002c, 0x80 },
{ 0x4004c, 0x0 },
{ 0x4006c, 0x0 },
{ 0x4000d, 0xe08 },
{ 0x4002d, 0xc1a },
{ 0x4004d, 0x0 },
{ 0x4006d, 0x0 },
{ 0x4000e, 0x623 },
{ 0x4002e, 0x1a },
{ 0x4004e, 0x0 },
{ 0x4006e, 0x0 },
{ 0x4000f, 0x4040 },
{ 0x4002f, 0x80 },
{ 0x4004f, 0x0 },
{ 0x4006f, 0x0 },
{ 0x40010, 0x2604 },
{ 0x40030, 0x15 },
{ 0x40050, 0x0 },
{ 0x40070, 0x0 },
{ 0x40011, 0x708 },
{ 0x40031, 0x5 },
{ 0x40051, 0x0 },
{ 0x40071, 0x2002 },
{ 0x40012, 0x8 },
{ 0x40032, 0x80 },
{ 0x40052, 0x0 },
{ 0x40072, 0x0 },
{ 0x40013, 0x2604 },
{ 0x40033, 0x1a },
{ 0x40053, 0x0 },
{ 0x40073, 0x0 },
{ 0x40014, 0x708 },
{ 0x40034, 0xa },
{ 0x40054, 0x0 },
{ 0x40074, 0x2002 },
{ 0x40015, 0x4040 },
{ 0x40035, 0x80 },
{ 0x40055, 0x0 },
{ 0x40075, 0x0 },
{ 0x40016, 0x60a },
{ 0x40036, 0x15 },
{ 0x40056, 0x1200 },
{ 0x40076, 0x0 },
{ 0x40017, 0x61a },
{ 0x40037, 0x15 },
{ 0x40057, 0x1300 },
{ 0x40077, 0x0 },
{ 0x40018, 0x60a },
{ 0x40038, 0x1a },
{ 0x40058, 0x1200 },
{ 0x40078, 0x0 },
{ 0x40019, 0x642 },
{ 0x40039, 0x1a },
{ 0x40059, 0x1300 },
{ 0x40079, 0x0 },
{ 0x4001a, 0x4808 },
{ 0x4003a, 0x880 },
{ 0x4005a, 0x0 },
{ 0x4007a, 0x0 },
{ 0x900a7, 0x0 },
{ 0x900a8, 0x790 },
{ 0x900a9, 0x11a },
{ 0x900aa, 0x8 },
{ 0x900ab, 0x7aa },
{ 0x900ac, 0x2a },
{ 0x900ad, 0x10 },
{ 0x900ae, 0x7b2 },
{ 0x900af, 0x2a },
{ 0x900b0, 0x0 },
{ 0x900b1, 0x7c8 },
{ 0x900b2, 0x109 },
{ 0x900b3, 0x10 },
{ 0x900b4, 0x2a8 },
{ 0x900b5, 0x129 },
{ 0x900b6, 0x8 },
{ 0x900b7, 0x370 },
{ 0x900b8, 0x129 },
{ 0x900b9, 0xa },
{ 0x900ba, 0x3c8 },
{ 0x900bb, 0x1a9 },
{ 0x900bc, 0xc },
{ 0x900bd, 0x408 },
{ 0x900be, 0x199 },
{ 0x900bf, 0x14 },
{ 0x900c0, 0x790 },
{ 0x900c1, 0x11a },
{ 0x900c2, 0x8 },
{ 0x900c3, 0x4 },
{ 0x900c4, 0x18 },
{ 0x900c5, 0xe },
{ 0x900c6, 0x408 },
{ 0x900c7, 0x199 },
{ 0x900c8, 0x8 },
{ 0x900c9, 0x8568 },
{ 0x900ca, 0x108 },
{ 0x900cb, 0x18 },
{ 0x900cc, 0x790 },
{ 0x900cd, 0x16a },
{ 0x900ce, 0x8 },
{ 0x900cf, 0x1d8 },
{ 0x900d0, 0x169 },
{ 0x900d1, 0x10 },
{ 0x900d2, 0x8558 },
{ 0x900d3, 0x168 },
{ 0x900d4, 0x70 },
{ 0x900d5, 0x788 },
{ 0x900d6, 0x16a },
{ 0x900d7, 0x1ff8 },
{ 0x900d8, 0x85a8 },
{ 0x900d9, 0x1e8 },
{ 0x900da, 0x50 },
{ 0x900db, 0x798 },
{ 0x900dc, 0x16a },
{ 0x900dd, 0x60 },
{ 0x900de, 0x7a0 },
{ 0x900df, 0x16a },
{ 0x900e0, 0x8 },
{ 0x900e1, 0x8310 },
{ 0x900e2, 0x168 },
{ 0x900e3, 0x8 },
{ 0x900e4, 0xa310 },
{ 0x900e5, 0x168 },
{ 0x900e6, 0xa },
{ 0x900e7, 0x408 },
{ 0x900e8, 0x169 },
{ 0x900e9, 0x6e },
{ 0x900ea, 0x0 },
{ 0x900eb, 0x68 },
{ 0x900ec, 0x0 },
{ 0x900ed, 0x408 },
{ 0x900ee, 0x169 },
{ 0x900ef, 0x0 },
{ 0x900f0, 0x8310 },
{ 0x900f1, 0x168 },
{ 0x900f2, 0x0 },
{ 0x900f3, 0xa310 },
{ 0x900f4, 0x168 },
{ 0x900f5, 0x1ff8 },
{ 0x900f6, 0x85a8 },
{ 0x900f7, 0x1e8 },
{ 0x900f8, 0x68 },
{ 0x900f9, 0x798 },
{ 0x900fa, 0x16a },
{ 0x900fb, 0x78 },
{ 0x900fc, 0x7a0 },
{ 0x900fd, 0x16a },
{ 0x900fe, 0x68 },
{ 0x900ff, 0x790 },
{ 0x90100, 0x16a },
{ 0x90101, 0x8 },
{ 0x90102, 0x8b10 },
{ 0x90103, 0x168 },
{ 0x90104, 0x8 },
{ 0x90105, 0xab10 },
{ 0x90106, 0x168 },
{ 0x90107, 0xa },
{ 0x90108, 0x408 },
{ 0x90109, 0x169 },
{ 0x9010a, 0x58 },
{ 0x9010b, 0x0 },
{ 0x9010c, 0x68 },
{ 0x9010d, 0x0 },
{ 0x9010e, 0x408 },
{ 0x9010f, 0x169 },
{ 0x90110, 0x0 },
{ 0x90111, 0x8b10 },
{ 0x90112, 0x168 },
{ 0x90113, 0x0 },
{ 0x90114, 0xab10 },
{ 0x90115, 0x168 },
{ 0x90116, 0x0 },
{ 0x90117, 0x1d8 },
{ 0x90118, 0x169 },
{ 0x90119, 0x80 },
{ 0x9011a, 0x790 },
{ 0x9011b, 0x16a },
{ 0x9011c, 0x18 },
{ 0x9011d, 0x7aa },
{ 0x9011e, 0x6a },
{ 0x9011f, 0xa },
{ 0x90120, 0x0 },
{ 0x90121, 0x1e9 },
{ 0x90122, 0x8 },
{ 0x90123, 0x8080 },
{ 0x90124, 0x108 },
{ 0x90125, 0xf },
{ 0x90126, 0x408 },
{ 0x90127, 0x169 },
{ 0x90128, 0xc },
{ 0x90129, 0x0 },
{ 0x9012a, 0x68 },
{ 0x9012b, 0x9 },
{ 0x9012c, 0x0 },
{ 0x9012d, 0x1a9 },
{ 0x9012e, 0x0 },
{ 0x9012f, 0x408 },
{ 0x90130, 0x169 },
{ 0x90131, 0x0 },
{ 0x90132, 0x8080 },
{ 0x90133, 0x108 },
{ 0x90134, 0x8 },
{ 0x90135, 0x7aa },
{ 0x90136, 0x6a },
{ 0x90137, 0x0 },
{ 0x90138, 0x8568 },
{ 0x90139, 0x108 },
{ 0x9013a, 0xb7 },
{ 0x9013b, 0x790 },
{ 0x9013c, 0x16a },
{ 0x9013d, 0x1f },
{ 0x9013e, 0x0 },
{ 0x9013f, 0x68 },
{ 0x90140, 0x8 },
{ 0x90141, 0x8558 },
{ 0x90142, 0x168 },
{ 0x90143, 0xf },
{ 0x90144, 0x408 },
{ 0x90145, 0x169 },
{ 0x90146, 0xc },
{ 0x90147, 0x0 },
{ 0x90148, 0x68 },
{ 0x90149, 0x0 },
{ 0x9014a, 0x408 },
{ 0x9014b, 0x169 },
{ 0x9014c, 0x0 },
{ 0x9014d, 0x8558 },
{ 0x9014e, 0x168 },
{ 0x9014f, 0x8 },
{ 0x90150, 0x3c8 },
{ 0x90151, 0x1a9 },
{ 0x90152, 0x3 },
{ 0x90153, 0x370 },
{ 0x90154, 0x129 },
{ 0x90155, 0x20 },
{ 0x90156, 0x2aa },
{ 0x90157, 0x9 },
{ 0x90158, 0x0 },
{ 0x90159, 0x400 },
{ 0x9015a, 0x10e },
{ 0x9015b, 0x8 },
{ 0x9015c, 0xe8 },
{ 0x9015d, 0x109 },
{ 0x9015e, 0x0 },
{ 0x9015f, 0x8140 },
{ 0x90160, 0x10c },
{ 0x90161, 0x10 },
{ 0x90162, 0x8138 },
{ 0x90163, 0x10c },
{ 0x90164, 0x8 },
{ 0x90165, 0x7c8 },
{ 0x90166, 0x101 },
{ 0x90167, 0x8 },
{ 0x90168, 0x0 },
{ 0x90169, 0x8 },
{ 0x9016a, 0x8 },
{ 0x9016b, 0x448 },
{ 0x9016c, 0x109 },
{ 0x9016d, 0xf },
{ 0x9016e, 0x7c0 },
{ 0x9016f, 0x109 },
{ 0x90170, 0x0 },
{ 0x90171, 0xe8 },
{ 0x90172, 0x109 },
{ 0x90173, 0x47 },
{ 0x90174, 0x630 },
{ 0x90175, 0x109 },
{ 0x90176, 0x8 },
{ 0x90177, 0x618 },
{ 0x90178, 0x109 },
{ 0x90179, 0x8 },
{ 0x9017a, 0xe0 },
{ 0x9017b, 0x109 },
{ 0x9017c, 0x0 },
{ 0x9017d, 0x7c8 },
{ 0x9017e, 0x109 },
{ 0x9017f, 0x8 },
{ 0x90180, 0x8140 },
{ 0x90181, 0x10c },
{ 0x90182, 0x0 },
{ 0x90183, 0x1 },
{ 0x90184, 0x8 },
{ 0x90185, 0x8 },
{ 0x90186, 0x4 },
{ 0x90187, 0x8 },
{ 0x90188, 0x8 },
{ 0x90189, 0x7c8 },
{ 0x9018a, 0x101 },
{ 0x90006, 0x0 },
{ 0x90007, 0x0 },
{ 0x90008, 0x8 },
{ 0x90009, 0x0 },
{ 0x9000a, 0x0 },
{ 0x9000b, 0x0 },
{ 0xd00e7, 0x400 },
{ 0x90017, 0x0 },
{ 0x9001f, 0x2a },
{ 0x90026, 0x6a },
{ 0x400d0, 0x0 },
{ 0x400d1, 0x101 },
{ 0x400d2, 0x105 },
{ 0x400d3, 0x107 },
{ 0x400d4, 0x10f },
{ 0x400d5, 0x202 },
{ 0x400d6, 0x20a },
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x2000b, 0x64 },
{ 0x2000c, 0xc8 },
{ 0x2000d, 0x7d0 },
{ 0x2000e, 0x2c },
{ 0x12000b, 0xc },
{ 0x12000c, 0x19 },
{ 0x12000d, 0xfa },
{ 0x12000e, 0x10 },
{ 0x22000b, 0x3 },
{ 0x22000c, 0x6 },
{ 0x22000d, 0x3e },
{ 0x22000e, 0x10 },
{ 0x9000c, 0x0 },
{ 0x9000d, 0x173 },
{ 0x9000e, 0x60 },
{ 0x9000f, 0x6110 },
{ 0x90010, 0x2152 },
{ 0x90011, 0xdfbd },
{ 0x90012, 0x60 },
{ 0x90013, 0x6152 },
{ 0x20010, 0x5a },
{ 0x20011, 0x3 },
{ 0x40080, 0xe0 },
{ 0x40081, 0x12 },
{ 0x40082, 0xe0 },
{ 0x40083, 0x12 },
{ 0x40084, 0xe0 },
{ 0x40085, 0x12 },
{ 0x140080, 0xe0 },
{ 0x140081, 0x12 },
{ 0x140082, 0xe0 },
{ 0x140083, 0x12 },
{ 0x140084, 0xe0 },
{ 0x140085, 0x12 },
{ 0x240080, 0xe0 },
{ 0x240081, 0x12 },
{ 0x240082, 0xe0 },
{ 0x240083, 0x12 },
{ 0x240084, 0xe0 },
{ 0x240085, 0x12 },
{ 0x400fd, 0xf },
{ 0x10011, 0x1 },
{ 0x10012, 0x1 },
{ 0x10013, 0x180 },
{ 0x10018, 0x1 },
{ 0x10002, 0x6209 },
{ 0x100b2, 0x1 },
{ 0x101b4, 0x1 },
{ 0x102b4, 0x1 },
{ 0x103b4, 0x1 },
{ 0x104b4, 0x1 },
{ 0x105b4, 0x1 },
{ 0x106b4, 0x1 },
{ 0x107b4, 0x1 },
{ 0x108b4, 0x1 },
{ 0x11011, 0x1 },
{ 0x11012, 0x1 },
{ 0x11013, 0x180 },
{ 0x11018, 0x1 },
{ 0x11002, 0x6209 },
{ 0x110b2, 0x1 },
{ 0x111b4, 0x1 },
{ 0x112b4, 0x1 },
{ 0x113b4, 0x1 },
{ 0x114b4, 0x1 },
{ 0x115b4, 0x1 },
{ 0x116b4, 0x1 },
{ 0x117b4, 0x1 },
{ 0x118b4, 0x1 },
{ 0x12011, 0x1 },
{ 0x12012, 0x1 },
{ 0x12013, 0x180 },
{ 0x12018, 0x1 },
{ 0x12002, 0x6209 },
{ 0x120b2, 0x1 },
{ 0x121b4, 0x1 },
{ 0x122b4, 0x1 },
{ 0x123b4, 0x1 },
{ 0x124b4, 0x1 },
{ 0x125b4, 0x1 },
{ 0x126b4, 0x1 },
{ 0x127b4, 0x1 },
{ 0x128b4, 0x1 },
{ 0x13011, 0x1 },
{ 0x13012, 0x1 },
{ 0x13013, 0x180 },
{ 0x13018, 0x1 },
{ 0x13002, 0x6209 },
{ 0x130b2, 0x1 },
{ 0x131b4, 0x1 },
{ 0x132b4, 0x1 },
{ 0x133b4, 0x1 },
{ 0x134b4, 0x1 },
{ 0x135b4, 0x1 },
{ 0x136b4, 0x1 },
{ 0x137b4, 0x1 },
{ 0x138b4, 0x1 },
{ 0x2003a, 0x2 },
{ 0xc0080, 0x2 },
{ 0xd0000, 0x1 },

+};



+struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {

{
/* P0 3200mts 1D */


.drate = 3200,


.fw_type = FW_1D_IMAGE,


.fsp_cfg = lpddr4_fsp0_cfg,


.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),


},
{
/* P1 400mts 1D */


.drate = 400,


.fw_type = FW_1D_IMAGE,


.fsp_cfg = lpddr4_fsp1_cfg,


.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),


},
{
/* P1 100mts 1D */


.drate = 100,


.fw_type = FW_1D_IMAGE,


.fsp_cfg = lpddr4_fsp2_cfg,


.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),


},
{
/* P0 3200mts 2D */


.drate = 3200,


.fw_type = FW_2D_IMAGE,


.fsp_cfg = lpddr4_fsp0_2d_cfg,


.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),


},

+};



+/* lpddr4 timing config params on EVK board */
+struct dram_timing_info dram_timing = {

.ddrc_cfg = lpddr4_ddrc_cfg,
.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
.ddrphy_cfg = lpddr4_ddrphy_cfg,
.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
.fsp_msg = lpddr4_dram_fsp_msg,
.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
.ddrphy_pie = lpddr4_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
.fsp_table = { 3200, 400, 100, },

+};
diff --git a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c
b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c
new file mode 100644
index 0000000000..ec68edaf69
--- /dev/null
+++ b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c
@@ -0,0 +1,1191 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*


Copyright 2018 NXP


*/


+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>



+#define WR_POST_EXT_3200  /* recommened to define */



+static struct dram_cfg_param lpddr4_ddrc_cfg[] = {

/* Start to config, default 3200mbps */
/* dis_dq=1, indicates no reads or writes are issued to SDRAM */
{ DDRC_DBG1(0), 0x00000001 },
/* selfref_en=1, SDRAM enter self-refresh state */
{ DDRC_PWRCTL(0), 0x00000001 },
{ DDRC_MSTR(0), 0xa3080020 },
{ DDRC_MSTR2(0), 0x00000000 },
{ DDRC_RFSHTMG(0), 0x006100E0 },
{ DDRC_INIT0(0), 0xC003061B },
{ DDRC_INIT1(0), 0x009D0000 },
{ DDRC_INIT3(0), 0x00D4002D },

+#ifdef WR_POST_EXT_3200  /* recommened to define */

{ DDRC_INIT4(0), 0x00330008 },

+#else

{ DDRC_INIT4(0), 0x00310008 },

+#endif

{ DDRC_INIT6(0), 0x0066004a },
{ DDRC_INIT7(0), 0x0006004a },

{ DDRC_DRAMTMG0(0), 0x1A201B22 },
{ DDRC_DRAMTMG1(0), 0x00060633 },
{ DDRC_DRAMTMG3(0), 0x00C0C000 },
{ DDRC_DRAMTMG4(0), 0x0F04080F },
{ DDRC_DRAMTMG5(0), 0x02040C0C },
{ DDRC_DRAMTMG6(0), 0x01010007 },
{ DDRC_DRAMTMG7(0), 0x00000401 },
{ DDRC_DRAMTMG12(0), 0x00020600 },
{ DDRC_DRAMTMG13(0), 0x0C100002 },
{ DDRC_DRAMTMG14(0), 0x000000E6 },
{ DDRC_DRAMTMG17(0), 0x00A00050 },

{ DDRC_ZQCTL0(0), 0x03200018 },
{ DDRC_ZQCTL1(0), 0x028061A8 },
{ DDRC_ZQCTL2(0), 0x00000000 },

{ DDRC_DFITMG0(0), 0x0497820A },
{ DDRC_DFITMG1(0), 0x00080303 },
{ DDRC_DFIUPD0(0), 0xE0400018 },
{ DDRC_DFIUPD1(0), 0x00DF00E4 },
{ DDRC_DFIUPD2(0), 0x80000000 },
{ DDRC_DFIMISC(0), 0x00000011 },
{ DDRC_DFITMG2(0), 0x0000170A },

{ DDRC_DBICTL(0), 0x00000001 },
{ DDRC_DFIPHYMSTR(0), 0x00000001 },

/* need be refined by ddrphy trained value */
{ DDRC_RANKCTL(0), 0x00000c99 },
{ DDRC_DRAMTMG2(0), 0x070E171a },

/* address mapping */
/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
{ DDRC_ADDRMAP0(0), 0x00000015 },
{ DDRC_ADDRMAP3(0), 0x00000000 },
/* addrmap_col_b10 addrmap_col_b11 set to de-activated (5-bit width)

*/

{ DDRC_ADDRMAP4(0), 0x00001F1F },
/* bank interleave */
/* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
{ DDRC_ADDRMAP1(0), 0x00080808 },
/* addrmap_row_b11 addrmap_row_b10_b2 addrmap_row_b1

addrmap_row_b0 */

{ DDRC_ADDRMAP5(0), 0x07070707 },
/* addrmap_row_b15 addrmap_row_b14 addrmap_row_b13

addrmap_row_b12 */

{ DDRC_ADDRMAP6(0), 0x08080707 },

/* 667mts frequency setting */
{ DDRC_FREQ1_DERATEEN(0), 0x0000000 },
{ DDRC_FREQ1_DERATEINT(0), 0x0800000 },
{ DDRC_FREQ1_RFSHCTL0(0), 0x0210000 },
{ DDRC_FREQ1_RFSHTMG(0), 0x014001E },
{ DDRC_FREQ1_INIT3(0), 0x0140009 },
{ DDRC_FREQ1_INIT4(0), 0x00310008 },
{ DDRC_FREQ1_INIT6(0), 0x0066004a },
{ DDRC_FREQ1_INIT7(0), 0x0006004a },
{ DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 },
{ DDRC_FREQ1_DRAMTMG1(0), 0x003040A },
{ DDRC_FREQ1_DRAMTMG2(0), 0x305080C },
{ DDRC_FREQ1_DRAMTMG3(0), 0x0505000 },
{ DDRC_FREQ1_DRAMTMG4(0), 0x3040203 },
{ DDRC_FREQ1_DRAMTMG5(0), 0x2030303 },
{ DDRC_FREQ1_DRAMTMG6(0), 0x2020004 },
{ DDRC_FREQ1_DRAMTMG7(0), 0x0000302 },
{ DDRC_FREQ1_DRAMTMG12(0), 0x0020310 },
{ DDRC_FREQ1_DRAMTMG13(0), 0xA100002 },
{ DDRC_FREQ1_DRAMTMG14(0), 0x0000020 },
{ DDRC_FREQ1_DRAMTMG17(0), 0x0220011 },
{ DDRC_FREQ1_ZQCTL0(0), 0x0A70005 },
{ DDRC_FREQ1_DFITMG0(0), 0x3858202 },
{ DDRC_FREQ1_DFITMG1(0), 0x0000404 },
{ DDRC_FREQ1_DFITMG2(0), 0x0000502 },

/* performance setting */
{ DDRC_ODTCFG(0), 0x0b060908 },
{ DDRC_ODTMAP(0), 0x00000000 },
{ DDRC_SCHED(0), 0x29511505 },
{ DDRC_SCHED1(0), 0x0000002c },
{ DDRC_PERFHPR1(0), 0x5900575b },
/* 150T starve and 0x90 max tran len */
{ DDRC_PERFLPR1(0), 0x90000096 },
/* 300T starve and 0x10 max tran len */
{ DDRC_PERFWR1(0), 0x1000012c },
{ DDRC_DBG0(0), 0x00000016 },
{ DDRC_DBG1(0), 0x00000000 },
{ DDRC_DBGCMD(0), 0x00000000 },
{ DDRC_SWCTL(0), 0x00000001 },
{ DDRC_POISONCFG(0), 0x00000011 },
{ DDRC_PCCFG(0), 0x00000111 },
{ DDRC_PCFGR_0(0), 0x000010f3 },
{ DDRC_PCFGW_0(0), 0x000072ff },
{ DDRC_PCTRL_0(0), 0x00000001 },
/* disable Read Qos*/
{ DDRC_PCFGQOS0_0(0), 0x00000e00 },
{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
/* disable Write Qos*/
{ DDRC_PCFGWQOS0_0(0), 0x00000e00 },
{ DDRC_PCFGWQOS1_0(0), 0x0000ffff },
{ DDRC_FREQ1_DERATEEN(0), 0x00000202 },
{ DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 },
{ DDRC_FREQ1_RFSHCTL0(0), 0x00618040 },
{ DDRC_FREQ1_RFSHTMG(0), 0x00610090 },

+};



+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {

{ 0x20110, 0x02 }, /* MapCAB0toDFI */
{ 0x20111, 0x03 }, /* MapCAB1toDFI */
{ 0x20112, 0x04 }, /* MapCAB2toDFI */
{ 0x20113, 0x05 }, /* MapCAB3toDFI */
{ 0x20114, 0x00 }, /* MapCAB4toDFI */
{ 0x20115, 0x01 }, /* MapCAB5toDFI */

/* Initialize PHY Configuration */
{ 0x1005f, 0x1ff },
{ 0x1015f, 0x1ff },
{ 0x1105f, 0x1ff },
{ 0x1115f, 0x1ff },
{ 0x1205f, 0x1ff },
{ 0x1215f, 0x1ff },
{ 0x1305f, 0x1ff },
{ 0x1315f, 0x1ff },

{ 0x11005f, 0x1ff },
{ 0x11015f, 0x1ff },
{ 0x11105f, 0x1ff },
{ 0x11115f, 0x1ff },
{ 0x11205f, 0x1ff },
{ 0x11215f, 0x1ff },
{ 0x11305f, 0x1ff },
{ 0x11315f, 0x1ff },

{ 0x21005f, 0x1ff },
{ 0x21015f, 0x1ff },
{ 0x21105f, 0x1ff },
{ 0x21115f, 0x1ff },
{ 0x21205f, 0x1ff },
{ 0x21215f, 0x1ff },
{ 0x21305f, 0x1ff },
{ 0x21315f, 0x1ff },

{ 0x55, 0x1ff },
{ 0x1055, 0x1ff },
{ 0x2055, 0x1ff },
{ 0x3055, 0x1ff },
{ 0x4055, 0x1ff },
{ 0x5055, 0x1ff },
{ 0x6055, 0x1ff },
{ 0x7055, 0x1ff },
{ 0x8055, 0x1ff },
{ 0x9055, 0x1ff },
{ 0x200c5, 0x19 },
{ 0x1200c5, 0x7 },
{ 0x2200c5, 0x7 },
{ 0x2002e, 0x2 },
{ 0x12002e, 0x1 },
{ 0x22002e, 0x2 },
{ 0x90204, 0x0 },
{ 0x190204, 0x0 },
{ 0x290204, 0x0 },

{ 0x20024, 0xe3 },
{ 0x2003a, 0x2 },
{ 0x120024, 0xa3 },
{ 0x2003a, 0x2 },
{ 0x220024, 0xa3 },
{ 0x2003a, 0x2 },

{ 0x20056, 0x3 },
{ 0x120056, 0xa },
{ 0x220056, 0xa },

{ 0x1004d, 0xe00 },
{ 0x1014d, 0xe00 },
{ 0x1104d, 0xe00 },
{ 0x1114d, 0xe00 },
{ 0x1204d, 0xe00 },
{ 0x1214d, 0xe00 },
{ 0x1304d, 0xe00 },
{ 0x1314d, 0xe00 },
{ 0x11004d, 0xe00 },
{ 0x11014d, 0xe00 },
{ 0x11104d, 0xe00 },
{ 0x11114d, 0xe00 },
{ 0x11204d, 0xe00 },
{ 0x11214d, 0xe00 },
{ 0x11304d, 0xe00 },
{ 0x11314d, 0xe00 },
{ 0x21004d, 0xe00 },
{ 0x21014d, 0xe00 },
{ 0x21104d, 0xe00 },
{ 0x21114d, 0xe00 },
{ 0x21204d, 0xe00 },
{ 0x21214d, 0xe00 },
{ 0x21304d, 0xe00 },
{ 0x21314d, 0xe00 },

{ 0x10049, 0xfbe },
{ 0x10149, 0xfbe },
{ 0x11049, 0xfbe },
{ 0x11149, 0xfbe },
{ 0x12049, 0xfbe },
{ 0x12149, 0xfbe },
{ 0x13049, 0xfbe },
{ 0x13149, 0xfbe },

{ 0x110049, 0xfbe },
{ 0x110149, 0xfbe },
{ 0x111049, 0xfbe },
{ 0x111149, 0xfbe },
{ 0x112049, 0xfbe },
{ 0x112149, 0xfbe },
{ 0x113049, 0xfbe },
{ 0x113149, 0xfbe },

{ 0x210049, 0xfbe },
{ 0x210149, 0xfbe },
{ 0x211049, 0xfbe },
{ 0x211149, 0xfbe },
{ 0x212049, 0xfbe },
{ 0x212149, 0xfbe },
{ 0x213049, 0xfbe },
{ 0x213149, 0xfbe },

{ 0x43, 0x63 },
{ 0x1043, 0x63 },
{ 0x2043, 0x63 },
{ 0x3043, 0x63 },
{ 0x4043, 0x63 },
{ 0x5043, 0x63 },
{ 0x6043, 0x63 },
{ 0x7043, 0x63 },
{ 0x8043, 0x63 },
{ 0x9043, 0x63 },

{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
{ 0x20008, 0x320 },
{ 0x120008, 0xa7 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
{ 0x200b2, 0x104 },
{ 0x10043, 0x5a1 },
{ 0x10143, 0x5a1 },
{ 0x11043, 0x5a1 },
{ 0x11143, 0x5a1 },
{ 0x12043, 0x5a1 },
{ 0x12143, 0x5a1 },
{ 0x13043, 0x5a1 },
{ 0x13143, 0x5a1 },
{ 0x1200b2, 0x104 },
{ 0x110043, 0x5a1 },
{ 0x110143, 0x5a1 },
{ 0x111043, 0x5a1 },
{ 0x111143, 0x5a1 },
{ 0x112043, 0x5a1 },
{ 0x112143, 0x5a1 },
{ 0x113043, 0x5a1 },
{ 0x113143, 0x5a1 },
{ 0x2200b2, 0x104 },
{ 0x210043, 0x5a1 },
{ 0x210143, 0x5a1 },
{ 0x211043, 0x5a1 },
{ 0x211143, 0x5a1 },
{ 0x212043, 0x5a1 },
{ 0x212143, 0x5a1 },
{ 0x213043, 0x5a1 },
{ 0x213143, 0x5a1 },
{ 0x200fa, 0x1 },
{ 0x1200fa, 0x1 },
{ 0x2200fa, 0x1 },
{ 0x20019, 0x1 },
{ 0x120019, 0x1 },
{ 0x220019, 0x1 },
{ 0x200f0, 0x600 },
{ 0x200f1, 0x0 },
{ 0x200f2, 0x4444 },
{ 0x200f3, 0x8888 },
{ 0x200f4, 0x5655 },
{ 0x200f5, 0x0 },
{ 0x200f6, 0x0 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
{ 0x2002d, 0x0 },
{ 0x12002d, 0x0 },
{ 0x22002d, 0x0 },

+};



+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg[] = {

{ 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
{ 0x54002, 0x0 },
{ 0x54003, 0xc80 },
{ 0x54004, 0x2 },
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
{ 0x54006, LPDDR4_PHY_VREF_VALUE },
{ 0x54007, 0x0 },
{ 0x54008, 0x131f },
{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
{ 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
{ 0x5400c, 0x0 },
{ 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
{ 0x5400e, 0x0 },
{ 0x5400f, 0x0 },
{ 0x54010, 0x0 },
{ 0x54011, 0x0 },
{ 0x54012, 0x310 },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
{ 0x54016, 0x0 },
{ 0x54017, 0x0 },
{ 0x54018, 0x0 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },


{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
{ 0x5401d, 0x0 },
{ 0x5401e, LPDDR4_MR22_RANK0 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },


{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
{ 0x54023, 0x0 },
{ 0x54024, LPDDR4_MR22_RANK1 },
{ 0x54025, 0x0 },
{ 0x54026, 0x0 },
{ 0x54027, 0x0 },
{ 0x54028, 0x0 },
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
{ 0x54030, 0x0 },
{ 0x54031, 0x0 },
{ 0x54032, 0xd400 },
{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
{ 0x54038, 0xd400 },
{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
{ 0x5403e, 0x0 },
{ 0x5403f, 0x0 },
{ 0x54040, 0x0 },
{ 0x54041, 0x0 },
{ 0x54042, 0x0 },
{ 0x54043, 0x0 },
{ 0x54044, 0x0 },
{ 0xd0000, 0x1 },

+};



+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg[] = {

{ 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
{ 0x54002, 0x1 },
{ 0x54003, 0x29c },
{ 0x54004, 0x2 },
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
{ 0x54006, LPDDR4_PHY_VREF_VALUE },
{ 0x54007, 0x0 },
{ 0x54008, 0x121f },
{ 0x54009, 0xc8 },
{ 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
{ 0x5400c, 0x0 },
{ 0x5400d, 0x0 },
{ 0x5400e, 0x0 },
{ 0x5400f, 0x0 },
{ 0x54010, 0x0 },
{ 0x54011, 0x0 },
{ 0x54012, 0x310 },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
{ 0x54016, 0x0 },
{ 0x54017, 0x0 },
{ 0x54018, 0x0 },
{ 0x54019, 0x914 },
{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },


{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
{ 0x5401e, 0x6 },
{ 0x5401f, 0x914 },
{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },


{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
{ 0x54023, 0x0 },
{ 0x54024, LPDDR4_MR22_RANK1 },
{ 0x54025, 0x0 },
{ 0x54026, 0x0 },
{ 0x54027, 0x0 },
{ 0x54028, 0x0 },
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
{ 0x54030, 0x0 },
{ 0x54031, 0x0 },
{ 0x54032, 0x1400 },
{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
{ 0x54037, 0x600 },
{ 0x54038, 0x1400 },
{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
{ 0x5403e, 0x0 },
{ 0x5403f, 0x0 },
{ 0x54040, 0x0 },
{ 0x54041, 0x0 },
{ 0x54042, 0x0 },
{ 0x54043, 0x0 },
{ 0xd0000, 0x1 },


+};



+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {

{ 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
{ 0x54002, 0x0 },
{ 0x54003, 0xc80 },
{ 0x54004, 0x2 },
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
{ 0x54006, LPDDR4_PHY_VREF_VALUE },
{ 0x54007, 0x0 },
{ 0x54008, 0x61 },
{ 0x54009, LPDDR4_HDT_CTL_2D },
{ 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
{ 0x5400c, 0x0 },
{ 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
{ 0x5400e, 0x0 },
{ 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
{ 0x54010, LPDDR4_2D_WEIGHT },
{ 0x54011, 0x0 },
{ 0x54012, 0x310 },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
{ 0x54016, 0x0 },
{ 0x54017, 0x0 },
{ 0x54018, 0x0 },
{ 0x54024, 0x5 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },


{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
{ 0x5401d, 0x0 },
{ 0x5401e, LPDDR4_MR22_RANK0 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },


{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
{ 0x54023, 0x0 },
{ 0x54024, LPDDR4_MR22_RANK1 },
{ 0x54025, 0x0 },
{ 0x54026, 0x0 },
{ 0x54027, 0x0 },
{ 0x54028, 0x0 },
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
{ 0x54030, 0x0 },
{ 0x54031, 0x0 },
{ 0x54032, 0xd400 },
{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
{ 0x54038, 0xd400 },
{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
{ 0x5403e, 0x0 },
{ 0x5403f, 0x0 },
{ 0x54040, 0x0 },
{ 0x54041, 0x0 },
{ 0x54042, 0x0 },
{ 0x54043, 0x0 },
{ 0x54044, 0x0 },
{ 0xd0000, 0x1 },


+};



+/* DRAM PHY init engine image */
+static struct dram_cfg_param lpddr4_phy_pie[] = {

{ 0xd0000, 0x0 },
{ 0x90000, 0x10 },
{ 0x90001, 0x400 },
{ 0x90002, 0x10e },
{ 0x90003, 0x0 },
{ 0x90004, 0x0 },
{ 0x90005, 0x8 },
{ 0x90029, 0xb },
{ 0x9002a, 0x480 },
{ 0x9002b, 0x109 },
{ 0x9002c, 0x8 },
{ 0x9002d, 0x448 },
{ 0x9002e, 0x139 },
{ 0x9002f, 0x8 },
{ 0x90030, 0x478 },
{ 0x90031, 0x109 },
{ 0x90032, 0x0 },
{ 0x90033, 0xe8 },
{ 0x90034, 0x109 },
{ 0x90035, 0x2 },
{ 0x90036, 0x10 },
{ 0x90037, 0x139 },
{ 0x90038, 0xb },
{ 0x90039, 0x7c0 },
{ 0x9003a, 0x139 },
{ 0x9003b, 0x44 },
{ 0x9003c, 0x630 },
{ 0x9003d, 0x159 },
{ 0x9003e, 0x14f },
{ 0x9003f, 0x630 },
{ 0x90040, 0x159 },
{ 0x90041, 0x47 },
{ 0x90042, 0x630 },
{ 0x90043, 0x149 },
{ 0x90044, 0x4f },
{ 0x90045, 0x630 },
{ 0x90046, 0x179 },
{ 0x90047, 0x8 },
{ 0x90048, 0xe0 },
{ 0x90049, 0x109 },
{ 0x9004a, 0x0 },
{ 0x9004b, 0x7c8 },
{ 0x9004c, 0x109 },
{ 0x9004d, 0x0 },
{ 0x9004e, 0x1 },
{ 0x9004f, 0x8 },
{ 0x90050, 0x0 },
{ 0x90051, 0x45a },
{ 0x90052, 0x9 },
{ 0x90053, 0x0 },
{ 0x90054, 0x448 },
{ 0x90055, 0x109 },
{ 0x90056, 0x40 },
{ 0x90057, 0x630 },
{ 0x90058, 0x179 },
{ 0x90059, 0x1 },
{ 0x9005a, 0x618 },
{ 0x9005b, 0x109 },
{ 0x9005c, 0x40c0 },
{ 0x9005d, 0x630 },
{ 0x9005e, 0x149 },
{ 0x9005f, 0x8 },
{ 0x90060, 0x4 },
{ 0x90061, 0x48 },
{ 0x90062, 0x4040 },
{ 0x90063, 0x630 },
{ 0x90064, 0x149 },
{ 0x90065, 0x0 },
{ 0x90066, 0x4 },
{ 0x90067, 0x48 },
{ 0x90068, 0x40 },
{ 0x90069, 0x630 },
{ 0x9006a, 0x149 },
{ 0x9006b, 0x10 },
{ 0x9006c, 0x4 },
{ 0x9006d, 0x18 },
{ 0x9006e, 0x0 },
{ 0x9006f, 0x4 },
{ 0x90070, 0x78 },
{ 0x90071, 0x549 },
{ 0x90072, 0x630 },
{ 0x90073, 0x159 },
{ 0x90074, 0xd49 },
{ 0x90075, 0x630 },
{ 0x90076, 0x159 },
{ 0x90077, 0x94a },
{ 0x90078, 0x630 },
{ 0x90079, 0x159 },
{ 0x9007a, 0x441 },
{ 0x9007b, 0x630 },
{ 0x9007c, 0x149 },
{ 0x9007d, 0x42 },
{ 0x9007e, 0x630 },
{ 0x9007f, 0x149 },
{ 0x90080, 0x1 },
{ 0x90081, 0x630 },
{ 0x90082, 0x149 },
{ 0x90083, 0x0 },
{ 0x90084, 0xe0 },
{ 0x90085, 0x109 },
{ 0x90086, 0xa },
{ 0x90087, 0x10 },
{ 0x90088, 0x109 },
{ 0x90089, 0x9 },
{ 0x9008a, 0x3c0 },
{ 0x9008b, 0x149 },
{ 0x9008c, 0x9 },
{ 0x9008d, 0x3c0 },
{ 0x9008e, 0x159 },
{ 0x9008f, 0x18 },
{ 0x90090, 0x10 },
{ 0x90091, 0x109 },
{ 0x90092, 0x0 },
{ 0x90093, 0x3c0 },
{ 0x90094, 0x109 },
{ 0x90095, 0x18 },
{ 0x90096, 0x4 },
{ 0x90097, 0x48 },
{ 0x90098, 0x18 },
{ 0x90099, 0x4 },
{ 0x9009a, 0x58 },
{ 0x9009b, 0xa },
{ 0x9009c, 0x10 },
{ 0x9009d, 0x109 },
{ 0x9009e, 0x2 },
{ 0x9009f, 0x10 },
{ 0x900a0, 0x109 },
{ 0x900a1, 0x5 },
{ 0x900a2, 0x7c0 },
{ 0x900a3, 0x109 },
{ 0x900a4, 0xd },
{ 0x900a5, 0x7c0 },
{ 0x900a6, 0x109 },
{ 0x900a7, 0x4 },
{ 0x900a8, 0x7c0 },
{ 0x900a9, 0x109 },
{ 0x40000, 0x811 },
{ 0x40020, 0x880 },
{ 0x40040, 0x0 },
{ 0x40060, 0x0 },
{ 0x40001, 0x4008 },
{ 0x40021, 0x83 },
{ 0x40041, 0x4f },
{ 0x40061, 0x0 },
{ 0x40002, 0x4040 },
{ 0x40022, 0x83 },
{ 0x40042, 0x51 },
{ 0x40062, 0x0 },
{ 0x40003, 0x811 },
{ 0x40023, 0x880 },
{ 0x40043, 0x0 },
{ 0x40063, 0x0 },
{ 0x40004, 0x720 },
{ 0x40024, 0xf },
{ 0x40044, 0x1740 },
{ 0x40064, 0x0 },
{ 0x40005, 0x16 },
{ 0x40025, 0x83 },
{ 0x40045, 0x4b },
{ 0x40065, 0x0 },
{ 0x40006, 0x716 },
{ 0x40026, 0xf },
{ 0x40046, 0x2001 },
{ 0x40066, 0x0 },
{ 0x40007, 0x716 },
{ 0x40027, 0xf },
{ 0x40047, 0x2800 },
{ 0x40067, 0x0 },
{ 0x40008, 0x716 },
{ 0x40028, 0xf },
{ 0x40048, 0xf00 },
{ 0x40068, 0x0 },
{ 0x40009, 0x720 },
{ 0x40029, 0xf },
{ 0x40049, 0x1400 },
{ 0x40069, 0x0 },
{ 0x4000a, 0xe08 },
{ 0x4002a, 0xc15 },
{ 0x4004a, 0x0 },
{ 0x4006a, 0x0 },
{ 0x4000b, 0x623 },
{ 0x4002b, 0x15 },
{ 0x4004b, 0x0 },
{ 0x4006b, 0x0 },
{ 0x4000c, 0x4028 },
{ 0x4002c, 0x80 },
{ 0x4004c, 0x0 },
{ 0x4006c, 0x0 },
{ 0x4000d, 0xe08 },
{ 0x4002d, 0xc1a },
{ 0x4004d, 0x0 },
{ 0x4006d, 0x0 },
{ 0x4000e, 0x623 },
{ 0x4002e, 0x1a },
{ 0x4004e, 0x0 },
{ 0x4006e, 0x0 },
{ 0x4000f, 0x4040 },
{ 0x4002f, 0x80 },
{ 0x4004f, 0x0 },
{ 0x4006f, 0x0 },
{ 0x40010, 0x2604 },
{ 0x40030, 0x15 },
{ 0x40050, 0x0 },
{ 0x40070, 0x0 },
{ 0x40011, 0x708 },
{ 0x40031, 0x5 },
{ 0x40051, 0x0 },
{ 0x40071, 0x2002 },
{ 0x40012, 0x8 },
{ 0x40032, 0x80 },
{ 0x40052, 0x0 },
{ 0x40072, 0x0 },
{ 0x40013, 0x2604 },
{ 0x40033, 0x1a },
{ 0x40053, 0x0 },
{ 0x40073, 0x0 },
{ 0x40014, 0x708 },
{ 0x40034, 0xa },
{ 0x40054, 0x0 },
{ 0x40074, 0x2002 },
{ 0x40015, 0x4040 },
{ 0x40035, 0x80 },
{ 0x40055, 0x0 },
{ 0x40075, 0x0 },
{ 0x40016, 0x60a },
{ 0x40036, 0x15 },
{ 0x40056, 0x1200 },
{ 0x40076, 0x0 },
{ 0x40017, 0x61a },
{ 0x40037, 0x15 },
{ 0x40057, 0x1300 },
{ 0x40077, 0x0 },
{ 0x40018, 0x60a },
{ 0x40038, 0x1a },
{ 0x40058, 0x1200 },
{ 0x40078, 0x0 },
{ 0x40019, 0x642 },
{ 0x40039, 0x1a },
{ 0x40059, 0x1300 },
{ 0x40079, 0x0 },
{ 0x4001a, 0x4808 },
{ 0x4003a, 0x880 },
{ 0x4005a, 0x0 },
{ 0x4007a, 0x0 },
{ 0x900aa, 0x0 },
{ 0x900ab, 0x790 },
{ 0x900ac, 0x11a },
{ 0x900ad, 0x8 },
{ 0x900ae, 0x7aa },
{ 0x900af, 0x2a },
{ 0x900b0, 0x10 },
{ 0x900b1, 0x7b2 },
{ 0x900b2, 0x2a },
{ 0x900b3, 0x0 },
{ 0x900b4, 0x7c8 },
{ 0x900b5, 0x109 },
{ 0x900b6, 0x10 },
{ 0x900b7, 0x10 },
{ 0x900b8, 0x109 },
{ 0x900b9, 0x10 },
{ 0x900ba, 0x2a8 },
{ 0x900bb, 0x129 },
{ 0x900bc, 0x8 },
{ 0x900bd, 0x370 },
{ 0x900be, 0x129 },
{ 0x900bf, 0xa },
{ 0x900c0, 0x3c8 },
{ 0x900c1, 0x1a9 },
{ 0x900c2, 0xc },
{ 0x900c3, 0x408 },
{ 0x900c4, 0x199 },
{ 0x900c5, 0x14 },
{ 0x900c6, 0x790 },
{ 0x900c7, 0x11a },
{ 0x900c8, 0x8 },
{ 0x900c9, 0x4 },
{ 0x900ca, 0x18 },
{ 0x900cb, 0xe },
{ 0x900cc, 0x408 },
{ 0x900cd, 0x199 },
{ 0x900ce, 0x8 },
{ 0x900cf, 0x8568 },
{ 0x900d0, 0x108 },
{ 0x900d1, 0x18 },
{ 0x900d2, 0x790 },
{ 0x900d3, 0x16a },
{ 0x900d4, 0x8 },
{ 0x900d5, 0x1d8 },
{ 0x900d6, 0x169 },
{ 0x900d7, 0x10 },
{ 0x900d8, 0x8558 },
{ 0x900d9, 0x168 },
{ 0x900da, 0x70 },
{ 0x900db, 0x788 },
{ 0x900dc, 0x16a },
{ 0x900dd, 0x1ff8 },
{ 0x900de, 0x85a8 },
{ 0x900df, 0x1e8 },
{ 0x900e0, 0x50 },
{ 0x900e1, 0x798 },
{ 0x900e2, 0x16a },
{ 0x900e3, 0x60 },
{ 0x900e4, 0x7a0 },
{ 0x900e5, 0x16a },
{ 0x900e6, 0x8 },
{ 0x900e7, 0x8310 },
{ 0x900e8, 0x168 },
{ 0x900e9, 0x8 },
{ 0x900ea, 0xa310 },
{ 0x900eb, 0x168 },
{ 0x900ec, 0xa },
{ 0x900ed, 0x408 },
{ 0x900ee, 0x169 },
{ 0x900ef, 0x6e },
{ 0x900f0, 0x0 },
{ 0x900f1, 0x68 },
{ 0x900f2, 0x0 },
{ 0x900f3, 0x408 },
{ 0x900f4, 0x169 },
{ 0x900f5, 0x0 },
{ 0x900f6, 0x8310 },
{ 0x900f7, 0x168 },
{ 0x900f8, 0x0 },
{ 0x900f9, 0xa310 },
{ 0x900fa, 0x168 },
{ 0x900fb, 0x1ff8 },
{ 0x900fc, 0x85a8 },
{ 0x900fd, 0x1e8 },
{ 0x900fe, 0x68 },
{ 0x900ff, 0x798 },
{ 0x90100, 0x16a },
{ 0x90101, 0x78 },
{ 0x90102, 0x7a0 },
{ 0x90103, 0x16a },
{ 0x90104, 0x68 },
{ 0x90105, 0x790 },
{ 0x90106, 0x16a },
{ 0x90107, 0x8 },
{ 0x90108, 0x8b10 },
{ 0x90109, 0x168 },
{ 0x9010a, 0x8 },
{ 0x9010b, 0xab10 },
{ 0x9010c, 0x168 },
{ 0x9010d, 0xa },
{ 0x9010e, 0x408 },
{ 0x9010f, 0x169 },
{ 0x90110, 0x58 },
{ 0x90111, 0x0 },
{ 0x90112, 0x68 },
{ 0x90113, 0x0 },
{ 0x90114, 0x408 },
{ 0x90115, 0x169 },
{ 0x90116, 0x0 },
{ 0x90117, 0x8b10 },
{ 0x90118, 0x168 },
{ 0x90119, 0x0 },
{ 0x9011a, 0xab10 },
{ 0x9011b, 0x168 },
{ 0x9011c, 0x0 },
{ 0x9011d, 0x1d8 },
{ 0x9011e, 0x169 },
{ 0x9011f, 0x80 },
{ 0x90120, 0x790 },
{ 0x90121, 0x16a },
{ 0x90122, 0x18 },
{ 0x90123, 0x7aa },
{ 0x90124, 0x6a },
{ 0x90125, 0xa },
{ 0x90126, 0x0 },
{ 0x90127, 0x1e9 },
{ 0x90128, 0x8 },
{ 0x90129, 0x8080 },
{ 0x9012a, 0x108 },
{ 0x9012b, 0xf },
{ 0x9012c, 0x408 },
{ 0x9012d, 0x169 },
{ 0x9012e, 0xc },
{ 0x9012f, 0x0 },
{ 0x90130, 0x68 },
{ 0x90131, 0x9 },
{ 0x90132, 0x0 },
{ 0x90133, 0x1a9 },
{ 0x90134, 0x0 },
{ 0x90135, 0x408 },
{ 0x90136, 0x169 },
{ 0x90137, 0x0 },
{ 0x90138, 0x8080 },
{ 0x90139, 0x108 },
{ 0x9013a, 0x8 },
{ 0x9013b, 0x7aa },
{ 0x9013c, 0x6a },
{ 0x9013d, 0x0 },
{ 0x9013e, 0x8568 },
{ 0x9013f, 0x108 },
{ 0x90140, 0xb7 },
{ 0x90141, 0x790 },
{ 0x90142, 0x16a },
{ 0x90143, 0x1f },
{ 0x90144, 0x0 },
{ 0x90145, 0x68 },
{ 0x90146, 0x8 },
{ 0x90147, 0x8558 },
{ 0x90148, 0x168 },
{ 0x90149, 0xf },
{ 0x9014a, 0x408 },
{ 0x9014b, 0x169 },
{ 0x9014c, 0xc },
{ 0x9014d, 0x0 },
{ 0x9014e, 0x68 },
{ 0x9014f, 0x0 },
{ 0x90150, 0x408 },
{ 0x90151, 0x169 },
{ 0x90152, 0x0 },
{ 0x90153, 0x8558 },
{ 0x90154, 0x168 },
{ 0x90155, 0x8 },
{ 0x90156, 0x3c8 },
{ 0x90157, 0x1a9 },
{ 0x90158, 0x3 },
{ 0x90159, 0x370 },
{ 0x9015a, 0x129 },
{ 0x9015b, 0x20 },
{ 0x9015c, 0x2aa },
{ 0x9015d, 0x9 },
{ 0x9015e, 0x0 },
{ 0x9015f, 0x400 },
{ 0x90160, 0x10e },
{ 0x90161, 0x8 },
{ 0x90162, 0xe8 },
{ 0x90163, 0x109 },
{ 0x90164, 0x0 },
{ 0x90165, 0x8140 },
{ 0x90166, 0x10c },
{ 0x90167, 0x10 },
{ 0x90168, 0x8138 },
{ 0x90169, 0x10c },
{ 0x9016a, 0x8 },
{ 0x9016b, 0x7c8 },
{ 0x9016c, 0x101 },
{ 0x9016d, 0x8 },
{ 0x9016e, 0x0 },
{ 0x9016f, 0x8 },
{ 0x90170, 0x8 },
{ 0x90171, 0x448 },
{ 0x90172, 0x109 },
{ 0x90173, 0xf },
{ 0x90174, 0x7c0 },
{ 0x90175, 0x109 },
{ 0x90176, 0x0 },
{ 0x90177, 0xe8 },
{ 0x90178, 0x109 },
{ 0x90179, 0x47 },
{ 0x9017a, 0x630 },
{ 0x9017b, 0x109 },
{ 0x9017c, 0x8 },
{ 0x9017d, 0x618 },
{ 0x9017e, 0x109 },
{ 0x9017f, 0x8 },
{ 0x90180, 0xe0 },
{ 0x90181, 0x109 },
{ 0x90182, 0x0 },
{ 0x90183, 0x7c8 },
{ 0x90184, 0x109 },
{ 0x90185, 0x8 },
{ 0x90186, 0x8140 },
{ 0x90187, 0x10c },
{ 0x90188, 0x0 },
{ 0x90189, 0x1 },
{ 0x9018a, 0x8 },
{ 0x9018b, 0x8 },
{ 0x9018c, 0x4 },
{ 0x9018d, 0x8 },
{ 0x9018e, 0x8 },
{ 0x9018f, 0x7c8 },
{ 0x90190, 0x101 },
{ 0x90006, 0x0 },
{ 0x90007, 0x0 },
{ 0x90008, 0x8 },
{ 0x90009, 0x0 },
{ 0x9000a, 0x0 },
{ 0x9000b, 0x0 },
{ 0xd00e7, 0x400 },
{ 0x90017, 0x0 },
{ 0x9001f, 0x2b },
{ 0x90026, 0x6c },
{ 0x400d0, 0x0 },
{ 0x400d1, 0x101 },
{ 0x400d2, 0x105 },
{ 0x400d3, 0x107 },
{ 0x400d4, 0x10f },
{ 0x400d5, 0x202 },
{ 0x400d6, 0x20a },
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
{ 0x2000b, 0x64 },
{ 0x2000c, 0xc8 },
{ 0x2000d, 0x7d0 },
{ 0x2000e, 0x2c },
{ 0x12000b, 0x14 },
{ 0x12000c, 0x29 },
{ 0x12000d, 0x1a1 },
{ 0x12000e, 0x10 },
{ 0x22000b, 0x3 },
{ 0x22000c, 0x6 },
{ 0x22000d, 0x3e },
{ 0x22000e, 0x10 },
{ 0x9000c, 0x0 },
{ 0x9000d, 0x173 },
{ 0x9000e, 0x60 },
{ 0x9000f, 0x6110 },
{ 0x90010, 0x2152 },
{ 0x90011, 0xdfbd },
{ 0x90012, 0x60 },
{ 0x90013, 0x6152 },
{ 0x20010, 0x5a },
{ 0x20011, 0x3 },
{ 0x40080, 0xe0 },
{ 0x40081, 0x12 },
{ 0x40082, 0xe0 },
{ 0x40083, 0x12 },
{ 0x40084, 0xe0 },
{ 0x40085, 0x12 },
{ 0x140080, 0xe0 },
{ 0x140081, 0x12 },
{ 0x140082, 0xe0 },
{ 0x140083, 0x12 },
{ 0x140084, 0xe0 },
{ 0x140085, 0x12 },
{ 0x240080, 0xe0 },
{ 0x240081, 0x12 },
{ 0x240082, 0xe0 },
{ 0x240083, 0x12 },
{ 0x240084, 0xe0 },
{ 0x240085, 0x12 },
{ 0x400fd, 0xf },
{ 0x10011, 0x1 },
{ 0x10012, 0x1 },
{ 0x10013, 0x180 },
{ 0x10018, 0x1 },
{ 0x10002, 0x6209 },
{ 0x100b2, 0x1 },
{ 0x101b4, 0x1 },
{ 0x102b4, 0x1 },
{ 0x103b4, 0x1 },
{ 0x104b4, 0x1 },
{ 0x105b4, 0x1 },
{ 0x106b4, 0x1 },
{ 0x107b4, 0x1 },
{ 0x108b4, 0x1 },
{ 0x11011, 0x1 },
{ 0x11012, 0x1 },
{ 0x11013, 0x180 },
{ 0x11018, 0x1 },
{ 0x11002, 0x6209 },
{ 0x110b2, 0x1 },
{ 0x111b4, 0x1 },
{ 0x112b4, 0x1 },
{ 0x113b4, 0x1 },
{ 0x114b4, 0x1 },
{ 0x115b4, 0x1 },
{ 0x116b4, 0x1 },
{ 0x117b4, 0x1 },
{ 0x118b4, 0x1 },
{ 0x12011, 0x1 },
{ 0x12012, 0x1 },
{ 0x12013, 0x180 },
{ 0x12018, 0x1 },
{ 0x12002, 0x6209 },
{ 0x120b2, 0x1 },
{ 0x121b4, 0x1 },
{ 0x122b4, 0x1 },
{ 0x123b4, 0x1 },
{ 0x124b4, 0x1 },
{ 0x125b4, 0x1 },
{ 0x126b4, 0x1 },
{ 0x127b4, 0x1 },
{ 0x128b4, 0x1 },
{ 0x13011, 0x1 },
{ 0x13012, 0x1 },
{ 0x13013, 0x180 },
{ 0x13018, 0x1 },
{ 0x13002, 0x6209 },
{ 0x130b2, 0x1 },
{ 0x131b4, 0x1 },
{ 0x132b4, 0x1 },
{ 0x133b4, 0x1 },
{ 0x134b4, 0x1 },
{ 0x135b4, 0x1 },
{ 0x136b4, 0x1 },
{ 0x137b4, 0x1 },
{ 0x138b4, 0x1 },
{ 0x20089, 0x1 },
{ 0x20088, 0x19 },
{ 0xc0080, 0x2 },
{ 0xd0000, 0x1 },

+};



+static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {

{
/* P0 3200mts 1D */


.drate = 3200,


.fw_type = FW_1D_IMAGE,


.fsp_cfg = lpddr4_fsp0_cfg,


.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),


},
{
/* P1 667mts 1D */


.drate = 667,


.fw_type = FW_1D_IMAGE,


.fsp_cfg = lpddr4_fsp1_cfg,


.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),


},
{
/* P0 3200mts 2D */


.drate = 3200,


.fw_type = FW_2D_IMAGE,


.fsp_cfg = lpddr4_fsp0_2d_cfg,


.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),


},

+};



+/* lpddr4 timing config params on EVK board */
+struct dram_timing_info dram_timing_b0 = {

.ddrc_cfg = lpddr4_ddrc_cfg,
.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
.ddrphy_cfg = lpddr4_ddrphy_cfg,
.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
.fsp_msg = lpddr4_dram_fsp_msg,
.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
.ddrphy_pie = lpddr4_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
/*
* this table must be initialized if DDRPHY bypass mode is


* not used: all fsp drate > 666MTS.


*/


.fsp_table = { 3200, 667, },

+};
diff --git a/board/freescale/imx8mq_evk/spl.c
b/board/freescale/imx8mq_evk/spl.c
new file mode 100644
index 0000000000..e6cbc34b0d
--- /dev/null
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*


Copyright 2018 NXP







SPDX-License-Identifier:	GPL-2.0+


*/


+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <spl.h>
+#include "../common/pfuze.h"



+DECLARE_GLOBAL_DATA_PTR;



+extern struct dram_timing_info dram_timing_b0;



+void spl_dram_init(void)
+{

/* ddr init */
if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
ddr_init(&dram_timing);


else
ddr_init(&dram_timing_b0);



+}



+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS |
PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {

.scl = {
.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,


.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,


.gp = IMX_GPIO_NR(5, 14),


},
.sda = {
.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,


.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,


.gp = IMX_GPIO_NR(5, 15),


},

+};



+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)



+int board_mmc_getcd(struct mmc *mmc)
+{

struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;

switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = 1;


break;


case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);


return ret;


}

return 1;

+}



+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS |
PAD_CTL_PUE | \

	 PAD_CTL_FSEL2)



+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)



+static iomux_v3_cfg_t const usdhc1_pads[] = {

IMX8MQ_PAD_SD1_CLK__USDHC1_CLK |

MUX_PAD_CTRL(USDHC_PAD_CTRL),

IMX8MQ_PAD_SD1_CMD__USDHC1_CMD |

MUX_PAD_CTRL(USDHC_PAD_CTRL),

IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 |

MUX_PAD_CTRL(USDHC_PAD_CTRL),

IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 |

MUX_PAD_CTRL(USDHC_PAD_CTRL),

IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 |

MUX_PAD_CTRL(USDHC_PAD_CTRL),

IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 |

MUX_PAD_CTRL(USDHC_PAD_CTRL),

IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 |

MUX_PAD_CTRL(USDHC_PAD_CTRL),

IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 |

MUX_PAD_CTRL(USDHC_PAD_CTRL),

IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 |

MUX_PAD_CTRL(USDHC_PAD_CTRL),

IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 |

MUX_PAD_CTRL(USDHC_PAD_CTRL),

IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 |

MUX_PAD_CTRL(NO_PAD_CTRL),
+};



+static iomux_v3_cfg_t const usdhc2_pads[] = {

IMX8MQ_PAD_SD2_CLK__USDHC2_CLK |

MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */

IMX8MQ_PAD_SD2_CMD__USDHC2_CMD |

MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */

IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 |

MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */

IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 |

MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */

IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 |

MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */

IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 |

MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */

IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 |

MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),

IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 |

MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};



+static struct fsl_esdhc_cfg usdhc_cfg[2] = {

{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},

+};



+int board_mmc_init(bd_t *bis)
+{

int i, ret;
/*
* According to the board_mmc_init() the following map is done:


* (U-Boot device node)    (Physical Port)


* mmc0                    USDHC1


* mmc1                    USDHC2


*/


for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {


case 0:


	init_clk_usdhc(0);


	usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);


	imx_iomux_v3_setup_multiple_pads(usdhc1_pads,


					 ARRAY_SIZE(usdhc1_pads));


	gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");


	gpio_direction_output(USDHC1_PWR_GPIO, 0);


	udelay(500);


	gpio_direction_output(USDHC1_PWR_GPIO, 1);


	break;


case 1:


	init_clk_usdhc(1);


	usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);


	imx_iomux_v3_setup_multiple_pads(usdhc2_pads,


					 ARRAY_SIZE(usdhc2_pads));


	gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");


	gpio_direction_output(USDHC2_PWR_GPIO, 0);


	udelay(500);


	gpio_direction_output(USDHC2_PWR_GPIO, 1);


	break;


default:


	printf("Warning: you configured more USDHC controllers(%d)



than supported by the board\n", i + 1);

	return -EINVAL;


}



ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);


if (ret)


	return ret;


}

return 0;

+}



+#ifdef CONFIG_POWER
+#define I2C_PMIC	0
+int power_init_board(void)
+{

struct pmic *p;
int ret;
unsigned int reg;

ret = power_pfuze100_init(I2C_PMIC);
if (ret)
return -ENODEV;



p = pmic_get("PFUZE100");
ret = pmic_probe(p);
if (ret)
return -ENODEV;



pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);

pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
if ((reg & 0x3f) != 0x18) {
reg &= ~0x3f;


reg |= 0x18;


pmic_reg_write(p, PFUZE100_SW3AVOL, reg);


}

ret = pfuze_mode_init(p, APS_PFM);
if (ret < 0)
return ret;



/* set SW3A standby mode to off */
pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
reg &= ~0xf;
reg |= APS_OFF;
pmic_reg_write(p, PFUZE100_SW3AMODE, reg);

return 0;

+}
+#endif



+void spl_board_init(void)
+{

puts("Normal Boot\n");

+}



+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{

/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);

return 0;

+}
+#endif



+void board_init_f(ulong dummy)
+{

int ret;

/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));

arch_cpu_init();

init_uart_clk(0);

board_early_init_f();

timer_init();

preloader_console_init();

/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);

ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);


hang();


}

enable_tzc380();

/* Adjust pmic voltage to 1.0V for 800M */
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);

power_init_board();

/* DDR initialization */
spl_dram_init();

board_init_r(NULL, 0);

+}
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
new file mode 100644
index 0000000000..f216d46a8f
--- /dev/null
+++ b/configs/imx8mq_evk_defconfig
@@ -0,0 +1,37 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TARGET_IMX8MQ_EVK=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk"
+CONFIG_OF_LIST="fsl-imx8mq-evk"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m
/imximage.cfg"
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+#CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd
.cfg"
+CONFIG_SPL=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_THERMAL=y
+CONFIG_FS_FAT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
new file mode 100644
index 0000000000..35f81152f2
--- /dev/null
+++ b/include/configs/imx8mq_evk.h
@@ -0,0 +1,252 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*


Copyright 2018 NXP


*/


+#ifndef __IMX8M_EVK_H
+#define __IMX8M_EVK_H



+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>



+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE			0x2000 /* 8K region */
+#endif



+#define CONFIG_SPL_TEXT_BASE		0x7E1000
+#define CONFIG_SPL_MAX_SIZE		(124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1



+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		0x187FF0
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_BSS_START_ADDR      0x00180000
+#define CONFIG_SPL_BSS_MAX_SIZE        0x2000	/* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START    0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE    0x80000	/* 512 KB */
+#define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF



+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR		0x182000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE



+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_PMIC
+#undef CONFIG_DM_PMIC_PFUZE100



+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */



+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG



+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+#endif



+#define CONFIG_REMAKE_ELF



+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT



+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS



+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD



+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_MII
+#define CONFIG_ETHPRIME                 "FEC"



+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+#define FEC_QUIRK_ENET_MAC



+#define CONFIG_PHY_GIGE
+#define IMX_FEC_BASE			0x30BE0000



+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#endif



+#define CONFIG_MFG_ENV_SETTINGS \

"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
"rdinit=/linuxrc " \


"g_mass_storage.stall=0 g_mass_storage.removable=1 " \


"g_mass_storage.idVendor=0x066F



g_mass_storage.idProduct=0x37FF "\

"g_mass_storage.iSerialNumber=\"\" "\


"clk_ignore_unused "\


"\0" \


"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffff\0" \
"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr}

${fdt_addr};\0" \
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\

CONFIG_MFG_ENV_SETTINGS \
"script=boot.scr\0" \
"image=Image\0" \
"console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
"fdt_addr=0x43000000\0"			\
"fdt_high=0xffffffffffffffff\0"		\
"boot_fdt=try\0" \
"fdt_file=fsl-imx8mq-evk.dtb\0" \
"initrd_addr=0x43800000\0"		\
"initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}

${script};\0" \

"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \


"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}

${image}\0" \

"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0"

\

"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \


"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \


	"if run loadfdt; then " \


		"booti ${loadaddr} - ${fdt_addr}; " \


	"else " \


		"echo WARN: Cannot load the DT; " \


	"fi; " \


"else " \


	"echo wait for boot; " \


"fi;\0" \


"netargs=setenv bootargs console=${console} " \
"root=/dev/nfs " \


"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \


"netboot=echo Booting from net ...; " \
"run netargs;  " \


"if test ${ip_dyn} = yes; then " \


	"setenv get_cmd dhcp; " \


"else " \


	"setenv get_cmd tftp; " \


"fi; " \


"${get_cmd} ${loadaddr} ${image}; " \


"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \


	"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \


		"booti ${loadaddr} - ${fdt_addr}; " \


	"else " \


		"echo WARN: Cannot load the DT; " \


	"fi; " \


"else " \


	"booti; " \


"fi;\0"




+#define CONFIG_BOOTCOMMAND \

  "mmc dev ${mmcdev}; if mmc rescan; then " \


   "if run loadbootscript; then " \


	   "run bootscript; " \


   "else " \


	   "if run loadimage; then " \


		   "run mmcboot; " \


	   "else run netboot; " \


	   "fi; " \


   "fi; " \


  "else booti ${loadaddr} - ${fdt_addr}; fi"




+/* Link Definitions */
+#define CONFIG_LOADADDR			0x40480000



+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR



+#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \

(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

+#define CONFIG_SYS_INIT_SP_ADDR \

(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)


+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET               (64 * SZ_64K)
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2
*/



+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (2 * 1024))









+#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define PHYS_SDRAM                      0x40000000
+#define PHYS_SDRAM_SIZE			0xC0000000 /* 3GB DDR */



+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END
   (CONFIG_SYS_MEMTEST_START + \

			(PHYS_SDRAM_SIZE >> 1))




+#define CONFIG_BAUDRATE			115200



+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE_ADDR



+/* Monitor Command Prompt */
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT		"u-boot=> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \

			sizeof(CONFIG_SYS_PROMPT) + 16)




+#define CONFIG_IMX_BOOTAUX



+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC



+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0



+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT



+#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1



+#define CONFIG_MXC_GPIO



+#define CONFIG_MXC_OCOTP
+#define CONFIG_CMD_FUSE



+/* I2C Configs */
+#define CONFIG_SYS_I2C_SPEED		  100000



+#define CONFIG_OF_SYSTEM_SETUP



+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_DM_PMIC
+#endif



+#endif
2.14.1

    