Re: [U-Boot] [PATCH v3 06/15] ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p

On 2019/7/16 上午2:21, Jagan Teki wrote:

Rename tsel_wr_select_p to tsel_wr_select_dq_p based on the bsp code.

No functionality change.

Signed-off-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: YouMin Chen cym@rock-chips.com

Reviewed-by: Kever Yang Kever.yang@rock-chips.com

Thanks,  - Kever

---

drivers/ram/rockchip/sdram_rk3399.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 85ff47f133..3ec32bdbc0 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -159,14 +159,14 @@ static void set_ds_odt(const struct chan_info *chan, u32 *denali_phy = chan->publ->denali_phy;

u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;

• u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;

• u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p; u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n; u32 reg_value;

  if (params->base.dramtype == LPDDR4) { tsel_rd_select_p = PHY_DRV_ODT_HI_Z;

• tsel_wr_select_p = PHY_DRV_ODT_40;
  

• tsel_wr_select_dq_p = PHY_DRV_ODT_40;
  

  ca_tsel_wr_select_p = PHY_DRV_ODT_40; tsel_idle_select_p = PHY_DRV_ODT_HI_Z;

@@ -176,7 +176,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_idle_select_n = PHY_DRV_ODT_240; } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240;

• tsel_wr_select_p = PHY_DRV_ODT_34_3;
  

• tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
  

  ca_tsel_wr_select_p = PHY_DRV_ODT_48; tsel_idle_select_p = PHY_DRV_ODT_240;

@@ -186,7 +186,7 @@ static void set_ds_odt(const struct chan_info *chan, tsel_idle_select_n = PHY_DRV_ODT_HI_Z; } else { tsel_rd_select_p = PHY_DRV_ODT_240;

• tsel_wr_select_p = PHY_DRV_ODT_34_3;
  

• tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
  

  ca_tsel_wr_select_p = PHY_DRV_ODT_34_3; tsel_idle_select_p = PHY_DRV_ODT_240;

@@ -210,7 +210,7 @@ static void set_ds_odt(const struct chan_info *chan, * for write cycles for DQ/DM */ reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |

•     (tsel_wr_select_dq_n << 8) | (tsel_wr_select_p << 12) |
  

•     (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
  

  (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);

@@ -250,7 +250,7 @@ static void set_ds_odt(const struct chan_info *chan,

/* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ clrsetbits_le32(&denali_phy[924], 0xff,

• 	tsel_wr_select_dq_n | (tsel_wr_select_p << 4));
  

• 	tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
  

  clrsetbits_le32(&denali_phy[925], 0xff, tsel_rd_select_n | (tsel_rd_select_p << 4));