Re: [U-Boot] [Patch v3 3/7] Add memory test feature for mpc85xx POST.

On Sep 28, 2010, at 5:20 PM, York Sun wrote:

The memory test is performed after DDR initialization when U-boot stills runs in flash and cache. On recent mpc85xx platforms, the total memory can be more than 2GB. To cover whole memory, it needs be mapped 2GB at a time using a sliding TLB window. After the testing, DDR is remapped with up to 2GB memory from the lowest address as normal.

If memory test fails, DDR DIMM SPD and DDR controller registers are dumped for further debugging.

Signed-off-by: York Sun yorksun@freescale.com

arch/powerpc/cpu/mpc85xx/cpu.c | 219 ++++++++++++++++++++++++++++++++++++++++ doc/README.fsl-ddr | 14 +++ 2 files changed, 233 insertions(+), 0 deletions(-)

applied to 85xx

- k