diff -purN orig/common/miiphyutil.c new/common/miiphyutil.c
--- orig/common/miiphyutil.c	2004-02-08 17:55:39.000000000 -0500
+++ new/common/miiphyutil.c	2004-03-12 10:39:07.000000000 -0500
@@ -135,11 +135,20 @@ int miiphy_speed (unsigned char addr)
 {
 	unsigned short reg;
 
+	if (miiphy_read (addr, PHY_1000BTSR, &reg)) {
+		printf ("PHY 1000BT Status read failed\n");
+	} else {
+		if (reg != 0xFFFF) {
+			if ((reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) !=0) {
+				return (_1000BASET);
+			}
+		}
+	}
+
 	if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
 		printf ("PHY speed1 read failed, assuming 10bT\n");
 		return (_10BASET);
 	}
-
 	if ((reg & PHY_ANLPAR_100) != 0) {
 		return (_100BASET);
 	} else {
@@ -156,6 +165,20 @@ int miiphy_duplex (unsigned char addr)
 {
 	unsigned short reg;
 
+
+	if (miiphy_read (addr, PHY_1000BTSR, &reg)) {
+		printf ("PHY 1000BT Status read failed\n");
+	} else {
+		if ( (reg != 0xFFFF) &&
+		     (reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) ) {
+			if ((reg & PHY_1000BTSR_1000FD) !=0) {
+				return (FULL);
+			} else {
+				return (HALF);
+			}
+		}
+	}
+
 	if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
 		printf ("PHY duplex read failed, assuming half duplex\n");
 		return (HALF);
diff -purN orig/cpu/ppc4xx/440gx_enet.c new/cpu/ppc4xx/440gx_enet.c
--- orig/cpu/ppc4xx/440gx_enet.c	2004-03-09 14:48:06.000000000 -0500
+++ new/cpu/ppc4xx/440gx_enet.c	2004-03-12 11:08:38.000000000 -0500
@@ -175,6 +175,100 @@ static void ppc_440x_eth_halt (struct et
 extern int phy_setup_aneg (unsigned char addr);
 extern int miiphy_reset (unsigned char addr);
 
+#if defined (CONFIG_440_GX)
+int ppc_440x_eth_setup_bridge(int devnum, bd_t * bis)
+{
+	unsigned long pfc1;
+	unsigned long zmiifer;
+	unsigned long rmiifer;
+
+	mfsdr(sdr_pfc1, pfc1);
+	pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
+
+	zmiifer = 0;
+	rmiifer = 0;
+
+	switch (pfc1) {
+	case 1:
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
+		break;
+	case 2:
+		zmiifer = ZMII_FER_SMII << ZMII_FER_V(0);
+		zmiifer = ZMII_FER_SMII << ZMII_FER_V(1);
+		zmiifer = ZMII_FER_SMII << ZMII_FER_V(2);
+		zmiifer = ZMII_FER_SMII << ZMII_FER_V(3);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
+		break;
+	case 3:
+		zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
+		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[3] = BI_PHYMODE_NONE;
+		break;
+	case 4:
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
+		break;
+	case 5:
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
+		break;
+	case 6:
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
+		rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[3] = BI_PHYMODE_RGMII;
+		break;
+	case 0:
+	default:
+		zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
+		rmiifer = 0x0;
+		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
+		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
+		break;
+	}
+
+	/* Ensure we setup mdio for this devnum and ONLY this devnum */
+	zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
+
+	out32 (ZMII_FER, zmiifer);
+	out32 (RGMII_FER, rmiifer);
+
+	return ((int)pfc1);
+
+}
+#endif
+
 static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
 {
 	int i;
@@ -187,11 +285,7 @@ static int ppc_440x_eth_init (struct eth
 	unsigned short devnum;
 	unsigned short reg_short;
 	sys_info_t sysinfo;
-#if defined (CONFIG_440_GX)
-	unsigned long pfc1;
-	unsigned long zmiifer;
-	unsigned long rmiifer;
-#endif
+	int ethgroup;
 
 	EMAC_440GX_HW_PST hw_p = dev->priv;
 
@@ -269,66 +363,7 @@ static int ppc_440x_eth_init (struct eth
 	udelay (100);
 
 #if defined(CONFIG_440_GX)
-	mfsdr(sdr_pfc1, pfc1);
-	pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
-
-	switch (pfc1) {
-	case 1:
-		zmiifer = (ZMII_FER_MDI | ZMII_FER_RMII) << ZMII_FER_V(devnum);
-		rmiifer = 0x0;
-		break;
-	case 2:
-		zmiifer = (ZMII_FER_MDI | ZMII_FER_SMII) << ZMII_FER_V(devnum);
-		rmiifer = 0x0;
-		break;
-	case 3:
-		if (devnum == 0) {
-			zmiifer = (ZMII_FER_MDI | ZMII_FER_RMII) << ZMII_FER_V(devnum);
-			rmiifer = 0x0;
-		} else if (devnum == 2) {
-			zmiifer = (ZMII_FER_MDI | ZMII_FER_RMII) << ZMII_FER_V(devnum);
-			rmiifer = RGMII_FER_RGMII << RGMII_FER_V(devnum);
-		} else { /* invalid case */
-			zmiifer = 0x0;
-			rmiifer = 0x0;
-		}
-		break;
-	case 4:
-		if ((devnum == 0) || (devnum == 1)) {
-			zmiifer = (ZMII_FER_MDI | ZMII_FER_SMII) << ZMII_FER_V (devnum);
-			rmiifer = 0x0;
-		} else { /* ((devnum == 2) || (devnum == 3)) */
-			zmiifer = (ZMII_FER_MDI/* | ZMII_FER_RMII */) << ZMII_FER_V (devnum);
-			rmiifer = RGMII_FER_RGMII << RGMII_FER_V (devnum);
-		}
-		break;
-	case 5:
-		if ((devnum == 0) || (devnum == 1) || (devnum == 2)) {
-			zmiifer = (ZMII_FER_MDI | ZMII_FER_SMII) << ZMII_FER_V (devnum);
-			rmiifer = 0x0;
-		} else {
-			zmiifer = (ZMII_FER_MDI | ZMII_FER_RMII) << ZMII_FER_V(devnum);
-			rmiifer = RGMII_FER_RGMII << RGMII_FER_V(devnum);
-		}
-		break;
-	case 6:
-		if ((devnum == 0) || (devnum == 1)) {
-			zmiifer = (ZMII_FER_MDI | ZMII_FER_SMII) << ZMII_FER_V (devnum);
-			rmiifer = 0x0;
-		} else {
-			zmiifer = (ZMII_FER_MDI | ZMII_FER_RMII) << ZMII_FER_V(devnum);
-			rmiifer = RGMII_FER_RGMII << RGMII_FER_V(devnum);
-		}
-		break;
-	case 0:
-	default:
-		zmiifer = (ZMII_FER_MDI | ZMII_FER_MII) << ZMII_FER_V(devnum);
-		rmiifer = 0x0;
-		break;
-	}
-
-	out32 (ZMII_FER, zmiifer);
-	out32 (RGMII_FER, rmiifer);
+	ethgroup = ppc_440x_eth_setup_bridge(devnum, bis);
 #else
 	if ((devnum == 0) || (devnum == 1)) {
 		out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
@@ -338,6 +373,7 @@ static int ppc_440x_eth_init (struct eth
 		out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
 				   (RGMII_FER_RGMII << RGMII_FER_V (3))));
 	}
+
 #endif
 	out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
 	__asm__ volatile ("eieio");
@@ -397,16 +433,17 @@ static int ppc_440x_eth_init (struct eth
 	/* Reset the phy */
 	miiphy_reset (reg);
 
+#if defined(CONFIG_440_GX)
 #if defined(CONFIG_CIS8201_PHY)
 	/*
 	 * Cicada 8201 PHY needs to have an extended register whacked
 	 * for RGMII mode.
 	 */
-	if ( ((devnum == 2) || (devnum ==3)) && (4 == pfc1) ) {
+	if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
 		miiphy_write (reg, 23, 0x1200);
 	}
 #endif
-
+#endif
 	/* Start/Restart autonegotiation */
 	phy_setup_aneg (reg);
 	udelay (1000);
@@ -451,7 +488,7 @@ static int ppc_440x_eth_init (struct eth
 
 	/* Set ZMII/RGMII speed according to the phy link speed */
 	reg = in32 (ZMII_SSR);
-	if (speed == 100)
+	if ( (speed == 100) || (speed == 1000) )
 		out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
 	else
 		out32 (ZMII_SSR,
@@ -620,7 +657,8 @@ static int ppc_440x_eth_init (struct eth
 
 	/* set speed */
- 	/* TBS: do 1GbE */
-	if (speed == _100BASET)
+	if (speed == _1000BASET)
+		mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
+	else if (speed == _100BASET)
 		mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
 	else
 		mode_reg = mode_reg & ~0x00C00000;	/* 10 MBPS */
diff -purN orig/include/miiphy.h new/include/miiphy.h
--- orig/include/miiphy.h	2003-10-08 18:33:01.000000000 -0400
+++ new/include/miiphy.h	2004-03-12 09:45:05.000000000 -0500
@@ -53,6 +53,7 @@ int  miiphy_link(unsigned char addr);
 
 /* phy seed setup */
 #define AUTO			99
+#define _1000BASET              1000
 #define _100BASET		100
 #define _10BASET		10
 #define HALF			22
@@ -67,6 +68,9 @@ int  miiphy_link(unsigned char addr);
 #define PHY_ANLPAR		0x05
 #define PHY_ANER		0x06
 #define PHY_ANNPTR		0x07
+#define PHY_ANLPNP              0x08
+#define PHY_1000BTCR            0x09
+#define PHY_1000BTSR            0x0A
 #define PHY_PHYSTS		0x10
 #define PHY_MIPSCR		0x11
 #define PHY_MIPGSR		0x12
@@ -113,4 +117,13 @@ int  miiphy_link(unsigned char addr);
 #define PHY_ANLPAR_10FD		0x0040
 #define PHY_ANLPAR_10		0x0020
 #define PHY_ANLPAR_100		0x0380	    /* we can run at 100 */
+
+/* PHY_1000BTSR */
+#define PHY_1000BTSR_MSCF       0x8000
+#define PHY_1000BTSR_MSCR       0x4000
+#define PHY_1000BTSR_LRS        0x2000
+#define PHY_1000BTSR_RRS        0x1000
+#define PHY_1000BTSR_1000FD     0x0800
+#define PHY_1000BTSR_1000HD     0x0400
+
 #endif
diff -purN orig/include/ppc440.h new/include/ppc440.h
