Hi Tom,
On 7/7/22 14:31, Tom Rini wrote:
On Thu, Jul 07, 2022 at 12:50:10PM +0200, Michal Simek wrote:
From: Christian Kohn christian.kohn@xilinx.com
The fclk-enable property is set to 0 which disables all FCLKs. Enable all FCLKs so they can be used as clock sources in the programmable logic.
Signed-off-by: Christian Kohn christian.kohn@xilinx.com Signed-off-by: Michal Simek michal.simek@amd.com
arch/arm/dts/zynq-7000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Since this (and the other patch today) are touching a common dtsi file, what is the status of these changes with upstream? Thanks.
Versal reset DT header is in Linux kernel already mmio-sram is enabled for zc702 board in kernel already but it is generic for all. #stream-id-cells - already removed in the kernel
And this fclk not sent to upstream linux yet.
Thanks, Michal