26 Nov
2013
26 Nov
'13
3:39 p.m.
On 11/21/2013 09:59 AM, Marc Zyngier wrote:
A CP15 instruction execution can be reordered, requiring an isb to be sure it is executed in program order.
Makes sense ;-) and works on the VExpress TC2.
Albert, Tom, please apply for v2014.01.
Acked-by: Andre Przywara andre.przywara@linaro.org
Signed-off-by: Marc Zyngier marc.zyngier@arm.com
arch/arm/cpu/armv7/nonsec_virt.S | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 29987cd..648066f 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -47,6 +47,7 @@ _secure_monitor: #endif
mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set)
isb
#ifdef CONFIG_ARMV7_VIRT mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value