Signed-off-by: Anatolij Gustschin agust@denx.de --- drivers/video/mb862xx.c | 96 ++++++++++++++++++++++++---------------------- include/mb862xx.h | 69 +++++++++++++++++++++++++++++++++ 2 files changed, 119 insertions(+), 46 deletions(-)
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c index 7bc3c9b..57b8667 100644 --- a/drivers/video/mb862xx.c +++ b/drivers/video/mb862xx.c @@ -70,29 +70,30 @@ unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 }; #define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val)) #endif
-#define HOST_RD_REG(off) rd_io((dev->frameAdrs + 0x01fc0000 + (off))) -#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + 0x01fc0000 + (off)), \ +#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off))) +#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \ (val)) -#define DISP_RD_REG(off) rd_io((dev->frameAdrs + 0x01fd0000 + (off))) -#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + 0x01fd0000 + (off)), \ +#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off))) +#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \ (val)) #define DE_RD_REG(off) rd_io((dev->dprBase + (off))) #define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
#if defined(CONFIG_VIDEO_CORALP) -#define DE_WR_FIFO(val) wr_io((dev->dprBase + (0x8400)), (val)) +#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val)) #else -#define DE_WR_FIFO(val) wr_io((dev->dprBase + (0x04a0)), (val)) +#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val)) #endif
-#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + 0x01fd0400 + \ +#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \ + (GC_DISP_BASE | GC_L0PAL0) + \ ((idx) << 2)), (val))
static void gdc_sw_reset (void) { GraphicDevice *dev = &mb862xx;
- HOST_WR_REG (0x002c, 0x00000001); + HOST_WR_REG (GC_SRST, 0x1); udelay (500); video_hw_init (); } @@ -107,7 +108,7 @@ static void de_wait (void) * Sync with software writes to framebuffer, * try to reset if engine locked */ - while (DE_RD_REG (0x0400) & 0x00000131) + while (DE_RD_REG (GC_CTR) & 0x00000131) if (lc-- < 0) { gdc_sw_reset (); printf ("gdc reset done after drawing engine lock.\n"); @@ -121,7 +122,7 @@ static void de_wait_slots (int slots) int lc = 0x10000;
/* Wait for free fifo slots */ - while (DE_RD_REG (0x0408) < slots) + while (DE_RD_REG (GC_IFCNT) < slots) if (lc-- < 0) { gdc_sw_reset (); printf ("gdc reset done after drawing engine lock.\n"); @@ -150,21 +151,21 @@ static void de_init (void) GraphicDevice *dev = &mb862xx; int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
- dev->dprBase = dev->frameAdrs + 0x01ff0000; + dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
/* Setup mode and fbbase, xres, fg, bg */ de_wait_slots (2); DE_WR_FIFO (0xf1010108); DE_WR_FIFO (cf | 0x0300); - DE_WR_REG (0x0440, 0x0000); - DE_WR_REG (0x0444, dev->winSizeX); - DE_WR_REG (0x0480, 0x0000); - DE_WR_REG (0x0484, 0x0000); + DE_WR_REG (GC_FBR, 0x0); + DE_WR_REG (GC_XRES, dev->winSizeX); + DE_WR_REG (GC_FC, 0x0); + DE_WR_REG (GC_BC, 0x0); /* Reset clipping */ - DE_WR_REG (0x0454, 0x0000); - DE_WR_REG (0x0458, dev->winSizeX); - DE_WR_REG (0x045c, 0x0000); - DE_WR_REG (0x0460, dev->winSizeY); + DE_WR_REG (GC_CXMIN, 0x0); + DE_WR_REG (GC_CXMAX, dev->winSizeX); + DE_WR_REG (GC_CYMIN, 0x0); + DE_WR_REG (GC_CYMAX, dev->winSizeY);
/* Clear framebuffer using drawing engine */ de_wait_slots (3); @@ -200,9 +201,9 @@ unsigned int pci_video_init (void) dev->pciBase = dev->frameAdrs;
/* Setup clocks and memory mode for Coral-P Eval. Board */ - HOST_WR_REG (0x0038, 0x00090000); + HOST_WR_REG (GC_CCF, 0x00090000); udelay (200); - HOST_WR_REG (0xfffc, 0x11d7fa13); + HOST_WR_REG (GC_MMR, 0x11d7fa13); udelay (100); return dev->frameAdrs; } @@ -301,36 +302,39 @@ unsigned int card_init (void) }
/* Setup dot clock (internal pll, division rate) */ - DISP_WR_REG (0x0100, div); + DISP_WR_REG (GC_DCM1, div); /* L0 init */ cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000; - DISP_WR_REG (0x0020, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 | + DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 | (dev->winSizeY - 1) | cf); - DISP_WR_REG (0x0024, 0x00000000); - DISP_WR_REG (0x0028, 0x00000000); - DISP_WR_REG (0x002c, 0x00000000); - DISP_WR_REG (0x0110, 0x00000000); - DISP_WR_REG (0x0114, 0x00000000); - DISP_WR_REG (0x0118, (dev->winSizeY - 1) << 16 | dev->winSizeX); + DISP_WR_REG (GC_L0OA0, 0x0); + DISP_WR_REG (GC_L0DA0, 0x0); + DISP_WR_REG (GC_L0DY_L0DX, 0x0); + DISP_WR_REG (GC_L0EM, 0x0); + DISP_WR_REG (GC_L0WY_L0WX, 0x0); + DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
/* Display timing init */ - DISP_WR_REG (0x0004, (dev->winSizeX + - res_mode->left_margin + - res_mode->right_margin + - res_mode->hsync_len - 1) << 16); - DISP_WR_REG (0x0008, (dev->winSizeX - 1) << 16 | (dev->winSizeX - 1)); - DISP_WR_REG (0x000c, (res_mode->vsync_len - 1) << 24 | - (res_mode->hsync_len - 1) << 16 | - (dev->winSizeX + res_mode->right_margin - 1)); - DISP_WR_REG (0x0010, (dev->winSizeY + res_mode->lower_margin + - res_mode->upper_margin + - res_mode->vsync_len - 1) << 16); - DISP_WR_REG (0x0014, (dev->winSizeY-1) << 16 | - (dev->winSizeY + res_mode->lower_margin - 1)); - DISP_WR_REG (0x0018, 0x00000000); - DISP_WR_REG (0x001c, dev->winSizeY << 16 | dev->winSizeX); + DISP_WR_REG (GC_HTP_A, (dev->winSizeX + + res_mode->left_margin + + res_mode->right_margin + + res_mode->hsync_len - 1) << 16); + DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 | + (dev->winSizeX - 1)); + DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 | + (res_mode->hsync_len - 1) << 16 | + (dev->winSizeX + + res_mode->right_margin - 1)); + DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin + + res_mode->upper_margin + + res_mode->vsync_len - 1) << 16); + DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 | + (dev->winSizeY + + res_mode->lower_margin - 1)); + DISP_WR_REG (GC_WY_WX, 0x0); + DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX); /* Display enable, L0 layer */ - DISP_WR_REG (0x0100, 0x80010000 | div); + DISP_WR_REG (GC_DCM1, 0x80010000 | div);
return dev->frameAdrs; } @@ -395,7 +399,7 @@ void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, GraphicDevice *dev = &mb862xx;
de_wait_slots (3); - DE_WR_REG (0x0480, color); + DE_WR_REG (GC_FC, color); DE_WR_FIFO (0x09410000); DE_WR_FIFO ((dst_y << 16) | dst_x); DE_WR_FIFO ((dim_y << 16) | dim_x); diff --git a/include/mb862xx.h b/include/mb862xx.h index 164305f..43f01e7 100644 --- a/include/mb862xx.h +++ b/include/mb862xx.h @@ -32,6 +32,75 @@ #define PCI_DEVICE_ID_CORAL_P 0x2019 #define PCI_DEVICE_ID_CORAL_PA 0x201E
+#define GC_HOST_BASE 0x01fc0000 +#define GC_DISP_BASE 0x01fd0000 +#define GC_DRAW_BASE 0x01ff0000 + +/* Host interface registers */ +#define GC_SRST 0x0000002c +#define GC_CCF 0x00000038 +#define GC_MMR 0x0000fffc + +/* + * Display Controller registers + * _A means the offset is aligned, we use these for boards + * with 8-/16-bit GDC access not working or buggy. + */ +#define GC_DCM0 0x00000000 +#define GC_HTP_A 0x00000004 +#define GC_HTP 0x00000006 +#define GC_HDB_HDP_A 0x00000008 +#define GC_HDP 0x00000008 +#define GC_HDB 0x0000000a +#define GC_VSW_HSW_HSP_A 0x0000000c +#define GC_HSP 0x0000000c +#define GC_HSW 0x0000000e +#define GC_VSW 0x0000000f +#define GC_VTR_A 0x00000010 +#define GC_VTR 0x00000012 +#define GC_VDP_VSP_A 0x00000014 +#define GC_VSP 0x00000014 +#define GC_VDP 0x00000016 +#define GC_WY_WX 0x00000018 +#define GC_WH_WW 0x0000001c +#define GC_L0M 0x00000020 +#define GC_L0OA0 0x00000024 +#define GC_L0DA0 0x00000028 +#define GC_L0DY_L0DX 0x0000002c +#define GC_L2M 0x00000040 +#define GC_L2OA0 0x00000044 +#define GC_L2DA0 0x00000048 +#define GC_L2OA1 0x0000004c +#define GC_L2DA1 0x00000050 +#define GC_L2DX 0x00000054 +#define GC_L2DY 0x00000056 +#define GC_DCM1 0x00000100 +#define GC_DCM2 0x00000104 +#define GC_DCM3 0x00000108 +#define GC_L0EM 0x00000110 +#define GC_L0WY_L0WX 0x00000114 +#define GC_L0WH_L0WW 0x00000118 +#define GC_L2EM 0x00000130 +#define GC_L2WX 0x00000134 +#define GC_L2WY 0x00000136 +#define GC_L2WW 0x00000138 +#define GC_L2WH 0x0000013a +#define GC_L0PAL0 0x00000400 + +/* Drawing registers */ +#define GC_CTR 0x00000400 +#define GC_IFCNT 0x00000408 +#define GC_FBR 0x00000440 +#define GC_XRES 0x00000444 +#define GC_CXMIN 0x00000454 +#define GC_CXMAX 0x00000458 +#define GC_CYMIN 0x0000045c +#define GC_CYMAX 0x00000460 +#define GC_FC 0x00000480 +#define GC_BC 0x00000484 +#define GC_FIFO 0x000004a0 +#define GC_GEO_FIFO 0x00008400 + typedef struct { unsigned int index; unsigned int value;