Extend board specific parameters to include write leveling start override Extend write leveling sample to 0xf Adding rcw overrid for quad-rank RDIMMs
Signed-off-by: York Sun yorksun@freescale.com --- board/freescale/corenet_ds/ddr.c | 120 +++++++++++++++++++++----------------- 1 files changed, 66 insertions(+), 54 deletions(-)
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 0eb290d..74339b5 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -145,6 +145,7 @@ typedef struct { u32 datarate_mhz_high; u32 n_ranks; u32 clk_adjust; + u32 wrlvl_start; u32 cpo; u32 write_data_delay; u32 force_2T; @@ -164,57 +165,57 @@ typedef struct { /* XXX: Single rank at 800 MHz is OK. */ const board_specific_parameters_t board_specific_parameters[][30] = { { - /* memory controller 0 */ - /* lo| hi| num| clk| cpo|wrdata|2T */ - /* mhz| mhz|ranks|adjst| | delay| */ - { 0, 333, 4, 5, 0xff, 2, 0}, - {334, 400, 4, 5, 0xff, 2, 0}, - {401, 549, 4, 5, 0xff, 2, 0}, - {550, 680, 4, 5, 0xff, 2, 0}, - {681, 850, 4, 5, 0xff, 2, 0}, - {851, 1050, 4, 5, 0xff, 2, 0}, - {1051, 1250, 4, 5, 0xff, 2, 0}, - {1251, 1350, 4, 5, 0xff, 2, 0}, - { 0, 333, 2, 5, 0xff, 2, 0}, - {334, 400, 2, 5, 0xff, 2, 0}, - {401, 549, 2, 5, 0xff, 2, 0}, - {550, 680, 2, 5, 0xff, 2, 0}, - {681, 850, 2, 5, 0xff, 2, 0}, - {851, 1050, 2, 5, 0xff, 2, 0}, - {1051, 1250, 2, 5, 0xff, 2, 0}, - {1251, 1350, 2, 5, 0xff, 2, 0}, - { 0, 333, 1, 5, 0xff, 2, 0}, - {334, 400, 1, 5, 0xff, 2, 0}, - {401, 549, 1, 5, 0xff, 2, 0}, - {550, 680, 1, 5, 0xff, 2, 0}, - {681, 850, 1, 5, 0xff, 2, 0} + /* memory controller 0 */ + /* lo| hi| num| clk| wrlvl | cpo |wrdata|2T */ + /* mhz| mhz|ranks|adjst| start | delay| */ + { 0, 333, 4, 5, 7, 0xff, 2, 0}, + {334, 400, 4, 5, 7, 0xff, 2, 0}, + {401, 549, 4, 5, 7, 0xff, 2, 0}, + {550, 680, 4, 5, 7, 0xff, 2, 0}, + {681, 850, 4, 5, 7, 0xff, 2, 0}, + {851, 1050, 4, 5, 7, 0xff, 2, 0}, + {1051, 1250, 4, 5, 8, 0xff, 2, 0}, + {1251, 1350, 4, 5, 9, 0xff, 2, 0}, + { 0, 333, 2, 5, 7, 0xff, 2, 0}, + {334, 400, 2, 5, 7, 0xff, 2, 0}, + {401, 549, 2, 5, 7, 0xff, 2, 0}, + {550, 680, 2, 5, 7, 0xff, 2, 0}, + {681, 850, 2, 5, 7, 0xff, 2, 0}, + {851, 1050, 2, 5, 7, 0xff, 2, 0}, + {1051, 1250, 2, 5, 7, 0xff, 2, 0}, + {1251, 1350, 2, 5, 7, 0xff, 2, 0}, + { 0, 333, 1, 5, 7, 0xff, 2, 0}, + {334, 400, 1, 5, 7, 0xff, 2, 0}, + {401, 549, 1, 5, 7, 0xff, 2, 0}, + {550, 680, 1, 5, 7, 0xff, 2, 0}, + {681, 850, 1, 5, 7, 0xff, 2, 0} },
{ - /* memory controller 1 */ - /* lo| hi| num| clk| cpo|wrdata|2T */ - /* mhz| mhz|ranks|adjst| | delay| */ - { 0, 333, 4, 5, 0xff, 2, 0}, - {334, 400, 4, 5, 0xff, 2, 0}, - {401, 549, 4, 5, 0xff, 2, 0}, - {550, 680, 4, 5, 0xff, 2, 0}, - {681, 850, 4, 5, 0xff, 2, 0}, - {851, 1050, 4, 5, 0xff, 2, 0}, - {1051, 1250, 4, 5, 0xff, 2, 0}, - {1251, 1350, 4, 5, 0xff, 2, 0}, - { 0, 333, 2, 5, 0xff, 2, 0}, - {334, 400, 2, 5, 0xff, 2, 0}, - {401, 549, 2, 5, 0xff, 2, 0}, - {550, 680, 2, 5, 0xff, 2, 0}, - {681, 850, 2, 5, 0xff, 2, 0}, - {851, 1050, 2, 5, 0xff, 2, 0}, - {1051, 1250, 2, 5, 0xff, 2, 0}, - {1251, 1350, 2, 5, 0xff, 2, 0}, - { 0, 333, 1, 5, 0xff, 2, 0}, - {334, 400, 1, 5, 0xff, 2, 0}, - {401, 549, 1, 5, 0xff, 2, 0}, - {550, 680, 1, 5, 0xff, 2, 0}, - {681, 850, 1, 5, 0xff, 2, 0} + /* memory controller 1 */ + /* lo| hi| num| clk| wrlvl | cpo |wrdata|2T */ + /* mhz| mhz|ranks|adjst| start | delay| */ + { 0, 333, 4, 5, 7, 0xff, 2, 0}, + {334, 400, 4, 5, 7, 0xff, 2, 0}, + {401, 549, 4, 5, 7, 0xff, 2, 0}, + {550, 680, 4, 5, 7, 0xff, 2, 0}, + {681, 850, 4, 5, 7, 0xff, 2, 0}, + {851, 1050, 4, 5, 7, 0xff, 2, 0}, + {1051, 1250, 4, 5, 8, 0xff, 2, 0}, + {1251, 1350, 4, 5, 9, 0xff, 2, 0}, + { 0, 333, 2, 5, 7, 0xff, 2, 0}, + {334, 400, 2, 5, 7, 0xff, 2, 0}, + {401, 549, 2, 5, 7, 0xff, 2, 0}, + {550, 680, 2, 5, 7, 0xff, 2, 0}, + {681, 850, 2, 5, 7, 0xff, 2, 0}, + {851, 1050, 2, 5, 7, 0xff, 2, 0}, + {1051, 1250, 2, 5, 7, 0xff, 2, 0}, + {1251, 1350, 2, 5, 7, 0xff, 2, 0}, + { 0, 333, 1, 5, 7, 0xff, 2, 0}, + {334, 400, 1, 5, 7, 0xff, 2, 0}, + {401, 549, 1, 5, 7, 0xff, 2, 0}, + {550, 680, 1, 5, 7, 0xff, 2, 0}, + {681, 850, 1, 5, 7, 0xff, 2, 0} } };
@@ -236,12 +237,12 @@ void fsl_ddr_board_options(memctl_options_t *popts, for (i = 0; i < num_params; i++) { if (ddr_freq >= pbsp->datarate_mhz_low && ddr_freq <= pbsp->datarate_mhz_high && - pdimm->n_ranks == pbsp->n_ranks) { + pdimm[0].n_ranks == pbsp->n_ranks) { popts->cpo_override = pbsp->cpo; popts->write_data_delay = pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; popts->twoT_en = pbsp->force_2T; - popts->wrlvl_start = pbsp->clk_adjust + 2; } pbsp++; } @@ -255,7 +256,8 @@ void fsl_ddr_board_options(memctl_options_t *popts, * Write leveling override */ popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xa; + popts->wrlvl_sample = 0xf; + /* * Rtt and Rtt_WR override */ @@ -267,9 +269,19 @@ void fsl_ddr_board_options(memctl_options_t *popts, /* DHC_EN =1, ODT = 60 Ohm */ popts->ddr_cdr1 = 0x80080000;
- popts->rcw_override = 1; - popts->rcw_1 = 0x000a5000; - popts->rcw_2 = 0x00100000; + /* override SPD values. rcw_2 should vary at differnt speed */ + if (pdimm[0].n_ranks == 4) { + popts->rcw_override = 1; + popts->rcw_1 = 0x000a5a00; + if (ddr_freq <= 800) + popts->rcw_2 = 0x00000000; + else if (ddr_freq <= 1066) + popts->rcw_2 = 0x00100000; + else if (ddr_freq <= 1333) + popts->rcw_2 = 0x00200000; + else + popts->rcw_2 = 0x00300000; + } }
phys_size_t initdram(int board_type)