Hello V, Aneesh,
V, Aneesh wrote:
Hello Heiko Schocher,
bounces@lists.denx.de] On Behalf Of Heiko Schocher +static inline void mmu_setup(void) +{
- static u32 __attribute__((aligned(16384))) page_table[4096];
- bd_t *bd = gd->bd;
- int i, j;
- u32 reg;
- /* Set up an identity-mapping for all 4GB, rw for everyone */
- for (i = 0; i < 4096; i++)
page_table[i] = i << 20 | (3 << 10) | 0x12;- /* Then, enable cacheable and bufferable for RAM only */
- for (j = 0; j < CONFIG_NR_DRAM_BANKS; j++) {
for (i = bd->bi_dram[j].start >> 20;i < (bd->bi_dram[j].start + bd->bi_dram[j].size)20;
i++) {page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;}- }
- /* Copy the page table address to cp15 */
- asm volatile("mcr p15, 0, %0, c2, c0, 0"
: : "r" (page_table) : "memory");- /* Set the access control to all-supervisor */
- asm volatile("mcr p15, 0, %0, c3, c0, 0"
: : "r" (~0));- /* and enable the mmu */
- reg = get_cr(); /* get control reg. */
- cp_delay();
- set_cr(reg | CR_M);
I think you need to invalidate caches, TLB, branch-prediction array etc before enabling MMU. I don't think the caches are guaranteed to be invalidated at power on reset.
Please find below some experimental(but working) code I had written for enabling MMU and caches for an internal project. It's written for the ARM RVCT tool chain. So, it will not compile straight away on GCC.
It has code for invalidating caches, TLB, Branch prediction array etc. Also, it uses macros for the bit fields in the SCTLR register. However, the L1 D$ cleaning is not generic. It assumes the size and organization of the L1 cache. arch/arm/cpu/armv7/omap3/cache.S has a more generic implementation of invalidating the entire L1 D$.
In case you find it useful, you are welcome to reuse any part of this code. If you want me to create a patch myself I am open to do that too.
Thanks!
I try to try out your suggestions, if you can make a patch (and try it on a plattform it would be great ;-)
bye, Heiko