This patch adds functions to enable/disable the power of USB host controller for EXYNOS5.
Signed-off-by: Vivek Gautam gautam.vivek@samsung.com Signed-off-by: Che-Liang Chiou clchiou@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com --- Chnages in v2: - Removed setting of SYSREG registers and moved to system.c. - Enabling and Disabling of USB_PHY_CTRL was moved to single function. Changes in v3: - Removed function to set PS_HOLD as it was not required for USB. - Renamed power_enable_usb_phy and exynos5_enable_usb_phy to set_usb_phy_ctrl and exynos5_set_usb_phy_ctrl. - Added defination for POWER_USB_HOST_PHY_CTRL_DISABLE. This patch is based on: USB: EXYNOS: Add ehci support.patch arch/arm/cpu/armv7/exynos/power.c | 22 ++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/power.h | 4 ++++ drivers/usb/host/ehci-exynos.c | 5 +++++ 3 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index c765304..e09917f 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -52,3 +52,25 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable) if (cpu_is_exynos4()) exynos4_mipi_phy_control(dev_index, enable); } + +void exynos5_set_usb_phy_ctrl(unsigned int enable) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + if (enable) { + /* Enabling USBHOST_PHY */ + setbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } else { + /* Disabling USBHOST_PHY */ + clrbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } +} + +void set_usb_phy_ctrl(unsigned int enable) +{ + if (cpu_is_exynos5()) + exynos5_set_usb_phy_ctrl(enable); +} diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index 4236beb..30aba16 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -855,4 +855,8 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable); #define EXYNOS_MIPI_PHY_SRESETN (1 << 1) #define EXYNOS_MIPI_PHY_MRESETN (1 << 2)
+void set_usb_phy_ctrl(unsigned int enable); + +#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0) +#define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0) #endif diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index 90d66d3..093b13d 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -25,6 +25,7 @@ #include <asm/arch/cpu.h> #include <asm/arch/ehci.h> #include <asm/arch/system.h> +#include <asm/arch/power.h> #include "ehci.h" #include "ehci-core.h"
@@ -33,6 +34,8 @@ static void setup_usb_phy(struct exynos_usb_phy *usb) { set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
+ set_usb_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN); + clrbits_le32(&usb->usbphyctrl0, HOST_CTRL0_FSEL_MASK | HOST_CTRL0_COMMONON_N | @@ -73,6 +76,8 @@ static void reset_usb_phy(struct exynos_usb_phy *usb) HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); + + set_usb_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE); }
/*