
20 Jan
2021
20 Jan
'21
8:49 a.m.
po 11. 1. 2021 v 14:01 odesÃlatel Michal Simek michal.simek@xilinx.com napsal:
Remove ifdef logic which is handled by preprocessor and move it link time optimization to get full compile code coverage.
Signed-off-by: Michal Simek michal.simek@xilinx.com
board/xilinx/common/board.c | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index cdc06a39ce58..9f651db734c7 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -324,25 +324,29 @@ void *board_fdt_blob_setup(void) { void *fdt_blob;
-#if !defined(CONFIG_VERSAL_NO_DDR) && !defined(CONFIG_ZYNQMP_NO_DDR)
fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
if (!IS_ENABLED(CONFIG_VERSAL_NO_DDR) &&
!IS_ENABLED(CONFIG_VERSAL_NO_DDR)) {
fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
if (fdt_magic(fdt_blob) == FDT_MAGIC)
return fdt_blob;
if (fdt_magic(fdt_blob) == FDT_MAGIC)
return fdt_blob;
debug("DTB is not passed via %p\n", fdt_blob);
-#endif
debug("DTB is not passed via %p\n", fdt_blob);
}
-#ifdef CONFIG_SPL_BUILD
/* FDT is at end of BSS unless it is in a different memory region */
if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
fdt_blob = (ulong *)&_image_binary_end;
else
fdt_blob = (ulong *)&__bss_end;
-#else
/* FDT is at end of image */
fdt_blob = (ulong *)&_end;
-#endif
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
/*
* FDT is at end of BSS unless it is in a different memory
* region
*/
if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
fdt_blob = (ulong *)&_image_binary_end;
else
fdt_blob = (ulong *)&__bss_end;
} else {
/* FDT is at end of image */
fdt_blob = (ulong *)&_end;
} if (fdt_magic(fdt_blob) == FDT_MAGIC) return fdt_blob;
-- 2.30.0
Applied. M
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs