On Tue, Jul 16, 2019 at 9:42 PM Joe Hershberger joe.hershberger@ni.com wrote:
On Tue, Jul 16, 2019 at 12:03 AM Ramon Fried rfried.dev@gmail.com wrote:
On Mon, Jul 15, 2019 at 11:48 PM Joe Hershberger joe.hershberger@ni.com wrote:
On Mon, Jul 15, 2019 at 3:26 PM Ramon Fried rfried.dev@gmail.com wrote:
On Mon, Jul 15, 2019 at 11:19 PM Ramon Fried rfried.dev@gmail.com wrote:
On Mon, Jul 15, 2019 at 9:31 PM Joe Hershberger joe.hershberger@ni.com wrote:
On Tue, Jun 11, 2019 at 10:51 AM Ramon Fried rfried.dev@gmail.com wrote: > > Few registers and bits were added by Cadence and > they were not updated in the headers. > Take the latest definitions as defined in Linux > header (5.1) that also includes some comments > about existing registers. > > One register was improperly named (UR), fix that.
This is breaking the build. "UR" is still referred to in drivers/net/macb.c line 805.
Did you build test this?
Well of course, but apparently I screwed this one in rebasing, prior to submit. Didn't run buildman afterwards. sorry. Will issue a revised patchset. Sorry. Ramon.
Actually, now that I look at this. it looks fine. the patch replaces the line you mentioned: https://patchwork.ozlabs.org/patch/1114041/ Can take a look ?
It addresses some of them, but not the ones a few lines below.
Just cherry-picked to a brand new master branch. there are no UR left on the file and it compiles correctly. Did you apply something else beforehand ?
One of them is even in the context of this patch...
- gem_writel(macb, UR, 0);
- gem_writel(macb, USRIO, 0);
#else #if defined(CONFIG_RGMII) || defined(CONFIG_RMII) gem_writel(macb, UR, GEM_BIT(RGMII));
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This right here, and another a few lines later.
Face palm I tested with SGMII, that's why it worked on my setup. I'll fix it shortly, sorry for the trouble :) Thanks, Ramon.