Hello Richard,
Richard Retanubun wrote:
From 9a7a9dfb1ed367b275bc19f7c40c98b63de75fb2 Mon Sep 17 00:00:00 2001 From: Richard Retanubun RichardRetanubun@RuggedCom.com Date: Wed, 18 Mar 2009 12:52:35 -0400 Subject: [PATCH] Update I2CFDR frequency divider 0x0E value from 192 to 204.
This patch changes the divider factor of 14 for I2CFDR. Through empirical experiments on a M5271EVB with a 25MHz osc, multiplied to 75MHz system frequency, the divider 0x0E that is supposed to be div-by-192, results in i2c clock of ~376 KHz (which is ~div-by-204). Using the alternate divider for div-by-192 (49) results in an i2c clock of ~390 KHz, a better clock approximation.
Signed-off-by: Richard Retanubun RichardRetanubun@RuggedCom.com
drivers/i2c/fsl_i2c.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index ce646fd..c61bf84 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -113,8 +113,8 @@ static const struct { {56, 41}, {64, 42}, {68, 7}, {72, 43}, {80, 8}, {80, 44}, {88, 9}, {96, 41}, {104, 10}, {112, 42}, {128, 11}, {128, 43},
- {144, 12}, {160, 13}, {160, 48}, {192, 14},
- {192, 49}, {224, 50}, {240, 15}, {256, 51},
- {144, 12}, {160, 13}, {160, 48}, {192, 49},
- {204, 14}, {224, 50}, {240, 15}, {256, 51}, {288, 16}, {320, 17}, {320, 52}, {384, 18}, {384, 53}, {448, 54}, {480, 19}, {512, 55}, {576, 20}, {640, 21}, {640, 56}, {768, 22},
Because I think this will go through the coldfire tree, you have my:
Acked-by: Heiko Schocher hs@denx.de
bye Heiko