Hi Aneesh,
I've enabled the L2 cache for Trats board. Please find results from performance tests. The test function as well as my way for enabling L2 are attached to this e-mail.
I simply left the default configuration (number of ways, associativity) as it is at Linux Kernel's driver.
Results:
test_l2_cache() performed once: L1 L2 TIME [seconds] OFF OFF 90,359 ON OFF 62,236 ON ON 61,687
L1 speedup: ~33 % L2 speedup (when compared to L1): < 1%
test_l2_cache() performed 5000 times: L1 L2 TIME [seconds] OFF OFF 444,9 ON OFF 320,55 ON ON 287,21
L1 speedup: ~28 % L2 speedup (when compared to L1): ~ 10%
Normal u-boot operation (from system startup - up till passing execution to kernel).
L1 L2 TIME [seconds] OFF OFF 1,813 ON OFF 1,552 ON ON 1,533
As one can observe, for normal u-boot operation there is no significant difference.
Have you had similar results with OMAP? Do you do more configuration when enabling the L2 at OMAP?
The assembly code presented below (armv7/omap-common/lowlevel_init.S) puzzles me a bit...
ENTRY(set_pl310_ctrl_reg) LDR r12, =0x102 @ Set PL310 control register - value in R0 .word 0xe1600070 @ SMC #0 - hand assembled @because -march=armv5 @ call ROM Code API to set control @ register ENDPROC(set_pl310_ctrl_reg)
Are there any special operations executed at "ROM Code API"?