We have changed to use dwc3 generic driver for Rockchip SoCs, so let amend dts to fix it and keep in line with Linux Kernel.
Signed-off-by: Frank Wang frank.wang@rock-chips.com --- arch/arm/dts/rk3399-evb.dts | 16 +++++++++++ arch/arm/dts/rk3399.dtsi | 54 ++++++++++++++++++++++--------------- 2 files changed, 49 insertions(+), 21 deletions(-)
diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index 694b0d08d6..10d5b9c08f 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -417,6 +417,14 @@ status = "disabled"; };
+&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + &u2phy0 { status = "okay"; }; @@ -439,6 +447,14 @@ status = "okay"; };
+&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 74f2c3d490..a6c8ba175f 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -388,28 +388,24 @@ status = "disabled"; };
- usbdrd3_0: usb@fe800000 { + usbdrd3_0: usb0 { compatible = "rockchip,rk3399-dwc3"; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, - <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; clock-names = "ref_clk", "suspend_clk", - "bus_clk", "aclk_usb3_rksoc_axi_perf", - "aclk_usb3", "grf_clk"; + "bus_clk", "grf_clk"; + power-domains = <&power RK3399_PD_USB3>; resets = <&cru SRST_A_USB3_OTG0>; reset-names = "usb3-otg"; status = "disabled";
- usbdrd_dwc3_0: dwc3 { + usbdrd_dwc3_0: dwc3@fe800000 { compatible = "snps,dwc3"; reg = <0x0 0xfe800000 0x0 0x100000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, - <&cru SCLK_USB3OTG0_SUSPEND>; - clock-names = "ref", "bus_early", "suspend"; dr_mode = "otg"; phys = <&u2phy0_otg>, <&tcphy0_usb3>; phy-names = "usb2-phy", "usb3-phy"; @@ -419,34 +415,32 @@ snps,dis_u2_susphy_quirk; snps,dis-del-phy-power-chg-quirk; snps,dis-tx-ipgap-linecheck-quirk; - power-domains = <&power RK3399_PD_USB3>; + snps,xhci-slow-suspend-quirk; + snps,xhci-trb-ent-quirk; + snps,usb3-warm-reset-on-resume-quirk; status = "disabled"; }; };
- usbdrd3_1: usb@fe900000 { + usbdrd3_1: usb1 { compatible = "rockchip,rk3399-dwc3"; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, - <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; + <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; clock-names = "ref_clk", "suspend_clk", - "bus_clk", "aclk_usb3_rksoc_axi_perf", - "aclk_usb3", "grf_clk"; + "bus_clk", "grf_clk"; + power-domains = <&power RK3399_PD_USB3>; resets = <&cru SRST_A_USB3_OTG1>; reset-names = "usb3-otg"; status = "disabled";
- usbdrd_dwc3_1: dwc3 { + usbdrd_dwc3_1: dwc3@fe900000 { compatible = "snps,dwc3"; reg = <0x0 0xfe900000 0x0 0x100000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, - <&cru SCLK_USB3OTG1_SUSPEND>; - clock-names = "ref", "bus_early", "suspend"; - dr_mode = "otg"; + dr_mode = "host"; phys = <&u2phy1_otg>, <&tcphy1_usb3>; phy-names = "usb2-phy", "usb3-phy"; phy_type = "utmi_wide"; @@ -455,7 +449,9 @@ snps,dis_u2_susphy_quirk; snps,dis-del-phy-power-chg-quirk; snps,dis-tx-ipgap-linecheck-quirk; - power-domains = <&power RK3399_PD_USB3>; + snps,xhci-slow-suspend-quirk; + snps,xhci-trb-ent-quirk; + snps,usb3-warm-reset-on-resume-quirk; status = "disabled"; }; }; @@ -1465,6 +1461,7 @@ tcphy0: phy@ff7c0000 { compatible = "rockchip,rk3399-typec-phy"; reg = <0x0 0xff7c0000 0x0 0x40000>; + #phy-cells = <1>; clocks = <&cru SCLK_UPHY0_TCPDCORE>, <&cru SCLK_UPHY0_TCPDPHY_REF>; clock-names = "tcpdcore", "tcpdphy-ref"; @@ -1476,6 +1473,13 @@ <&cru SRST_P_UPHY0_TCPHY>; reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; rockchip,grf = <&grf>; + rockchip,typec-conn-dir = <0xe580 0 16>; + rockchip,usb3tousb2-en = <0xe580 3 19>; + rockchip,usb3-host-disable = <0x2434 0 16>; + rockchip,usb3-host-port = <0x2434 12 28>; + rockchip,external-psm = <0xe588 14 30>; + rockchip,pipe-status = <0xe5c0 0 0>; + rockchip,uphy-dp-sel = <0x6268 19 19>; status = "disabled";
tcphy0_dp: dp-port { @@ -1490,6 +1494,7 @@ tcphy1: phy@ff800000 { compatible = "rockchip,rk3399-typec-phy"; reg = <0x0 0xff800000 0x0 0x40000>; + #phy-cells = <1>; clocks = <&cru SCLK_UPHY1_TCPDCORE>, <&cru SCLK_UPHY1_TCPDPHY_REF>; clock-names = "tcpdcore", "tcpdphy-ref"; @@ -1501,6 +1506,13 @@ <&cru SRST_P_UPHY1_TCPHY>; reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; rockchip,grf = <&grf>; + rockchip,typec-conn-dir = <0xe58c 0 16>; + rockchip,usb3tousb2-en = <0xe58c 3 19>; + rockchip,usb3-host-disable = <0x2444 0 16>; + rockchip,usb3-host-port = <0x2444 12 28>; + rockchip,external-psm = <0xe594 14 30>; + rockchip,pipe-status = <0xe5c0 16 16>; + rockchip,uphy-dp-sel = <0x6268 3 19>; status = "disabled";
tcphy1_dp: dp-port {