Re: [U-Boot] [PATCH] armv8:fsl-layerscape: Add registers space defination for CCI-400 bus

On 02/01/2017 05:49 AM, Ashish Kumar wrote:

CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters.

This patch add new CONFIG defination and move existing register space definaton of CCI-400 bus from from immap_lsch2 to fsl_immap, so that it can be used for both chasis 2 and chasis 3.

Please don't indent the commit message.

Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Signed-off-by: Ashish Kumar Ashish.Kumar@nxp.com

---

README | 9 ++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1 + arch/arm/cpu/armv8/fsl-layerscape/soc.c | 1 + .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 48 -------------------- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + include/fsl_immap.h | 51 ++++++++++++++++++++++ 7 files changed, 69 insertions(+), 48 deletions(-)

diff --git a/README b/README index a95348a..f70ad49 100644 --- a/README +++ b/README @@ -315,6 +315,15 @@ Many of the options are named exactly as the corresponding Linux kernel configuration options. The intention is to make it easier to build a config tool - later.

+- ARM Platform Bus Type(CCI):

• CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
  

• provides full cache coherency between two clusters of multi-core
  

• CPUs and I/O coherency for devices and I/O masters
  

• CONFIG_SYS_FSL_HAS_CCI400
  

• Defined For SoC that has cache coherent interconnect
  

• CCN-400
  
  

The following options need to be configured:

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 47897f4..0ea43c6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -7,6 +7,7 @@ config ARCH_LS1012A select SYS_FSL_ERRATUM_A010315 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F

• select SYS_FSL_HAS_CCI400

config ARCH_LS1043A bool @@ -26,6 +27,7 @@ config ARCH_LS1043A select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F

• select SYS_FSL_HAS_CCI400

config ARCH_LS1046A bool @@ -44,6 +46,7 @@ config ARCH_LS1046A select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F

• select SYS_FSL_HAS_CCI400

config ARCH_LS2080A bool @@ -184,6 +187,9 @@ config SYS_FSL_IFC_BANK_COUNT config SYS_FSL_HAS_DP_DDR bool

+config SYS_FSL_HAS_CCI400

• bool

Please try to keep the config option in order. Easier to search later.

York