Sam,
On Tue, 2007-03-06 at 21:19 +0800, Sam Song wrote:
Hi all,
I'd like to implemente BITBANGMII for MPC8548 with a external Marvell 88E1111 PHY as RGMII interface. The reason was that this board's MII control lines MDC was broken as HIGH level always(Sure, it worked right with tsec driver). So u-boot reported no PHY found - Bad news:-(
I followed EP8248 BITBANGMII way to use CPLD to implementate BITBANGMII but couldn't read PHY register correctly - PHY ID still unknown.
Time to reach into your engineering tool bag.
I wonder whether eTSEC controller can use BITBANGMII way to work with outside PHY. Seems that no MII support eTSEC driver not functional.
MDIO comms are always (well, maybe not always) done in software. By this I mean that while the MDIO controllers are part of the Ethernet controllers, coupling is loose. You should be able to bitbang this provided the physical wires exist between the CPLD and the PHY. I guess white-wiring the TSEC's MDC line isn't an option?
<board>.h #define CONFIG_BITBANGMII
#define MDIO_PORT 0 /* Not used - implemented in BCSR */ #define MDIO_ACTIVE \ (*(vu_char *)(CFG_BCSR + 83) |= 0x01) #define MDIO_TRISTATE \ (*(vu_char *)(CFG_BCSR + 83) &= 0xFE) #define MDIO_READ \ ((*(vu_char *)(CFG_BCSR + 83) & 1) != 0)
#define MDIO(bit) \ if(bit) *(vu_char *)(CFG_BCSR + 83) |= 0x01; \ else *(vu_char *)(CFG_BCSR + 83) &= 0xFE
#define MDC(bit) \ if(bit) *(vu_char *)(CFG_BCSR + 83) |= 0x02; \ else *(vu_char *)(CFG_BCSR + 83) &= 0xFD #define MIIDELAY udelay(1)
Stylistically, this leaves a lot to be desired, but if register 83 (better to use hex here) really maps to the MDC and MDIO pins, it should work.
drivers/tsec.c
<SNIP>
Am I on the right track?
Before messing with the TSEC driver, try talking with the PHY using the 'mii' U-boot commands. Also, pull out your oscilloscope and check that the lines are toggling as you want. Once you're confident Bitbanged-MII works, integrate it into TSEC.
regards, Ben