From: Quentin Schulz quentin.schulz@cherry.de
On px30-ringneck the FIT payload is located at sector 0x200 compared to the more Rockchip common sector 0x4000 offset: SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
Because FIT payload is located at sector 0x200 and the TPL+SPL is located at sector 64, the combined size of TPL+SPL cannot take up more than 224KiB: (0x200 - 64) x 512 = 0x38000 (224 KiB)
Adjust SPL_PAD_TO to match the used 0x200 sector offset.
While at it, update the px30-ringneck-u-boot.dtsi to remove the now unnecessary override of simple-bin:fit:offset since SPL_PAD_TO matches with the current formula.
Reviewed-by: Kever Yang kever.yang@rock-chips.com Signed-off-by: Quentin Schulz quentin.schulz@cherry.de --- arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi | 8 -------- configs/ringneck-px30_defconfig | 2 +- 2 files changed, 1 insertion(+), 9 deletions(-)
diff --git a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi index e04766ad09c..29ea2763636 100644 --- a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi +++ b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi @@ -15,14 +15,6 @@ }; };
-&binman { - simple-bin { - fit { - offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>; - }; - }; -}; - &emmc_clk { bootph-all; }; diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index dedf35d4347..a22d25e0089 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -25,7 +25,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 -CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_PAD_TO=0x38000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set