Hi Laurent,
you cannot imagine how many grey hair this bit naming and numbering convention cost me. I learned to never use D0/7 when meaning MSB/LSB:-)
On Wednesday 22 August 2007 09:28, Laurent Pinchart wrote:
I must respectfully disagree. In my design, if I mirror in the code the FPGA does NOT load. In a PPC, D0 is the MSB, NOT the LSB. In a Spartan 3 FPGA, D0 is the MSB, NOT the LSB. Therefore if you connect your bus straight across between the PPC and the Spartan 3 FPGA, AND do mirroring in the code, your FPGA will not load.
I got a similar design, except that D0-D7 on the PPC are connected to D7-D0 on the FPGA. I'll go scold our hardware engineer :-)
Sometimes it's even worth as softwa/orkers to review schematics when you know that you will get the board on your desk for writing software :-) (But do not sign anything or the hardware engineer will scold you afterwards.)
With a properly connected bus between the processor and the FPGA, bit reversal is thus not needed when loading a .bit file (fpga loadb) or a non mirrored PROM file (fpga load).
BTW, you can even load a .bit file using fpga load because the FPGA will discard the header.
For hardware with bit mirroring on the bus, I suggest either using a mirrored PROM file or mirroring the bit in the data write callback. I thus vote for
Ack
removing bit mirroring in fpga_loadbitstream() and adding an explanation of
Ack. So all the malloc and the timeconsuming loop code will disappear. Yippi!
this issue (either in the code or in the documentation) to prevent hardware mistakes in future designs.
Good idea. But do you think that hardware engineers will read through the cmd_fpga.c file?
I will cleanup my changes and submit a patch soon.
Matthias