This series adds support for enhanced SPI modes. It was tested on a K210 (DWC SSI with QSPI flash).
If anyone has a designware device with QSPI flash attached (especially a DW SSI APB device), I'd greatly appreciate them testing out this patch series. Given that there has been no testing of v2 over the past month, I don't think lack of testing should hold up this series.
Changes in v3: - Dropped merged patches - Rebased on u-boot/master
Changes in v2: - Add more information to exec_op debug message - Actually mask interrupts - Merge CAP_{DUAL,QUAD,OCTAL} into CAP_ENHANCED - Fix some inconsistencies in register naming and usage - Moved some hunks between commits so things make more sense
Sean Anderson (10): mtd: spi-mem: Export spi_mem_default_supports_op spi: spi-mem: Add debug message for spi-mem ops spi: dw: Log status register on timeout spi: dw: Actually mask interrupts spi: dw: Switch to capabilities spi: dw: Rewrite poll_transfer logic spi: dw: Add ENHANCED cap spi: dw: Define registers for enhanced mode spi: dw: Support enhanced SPI spi: dw: Support clock stretching
drivers/spi/designware_spi.c | 647 ++++++++++++++++++++++++----------- drivers/spi/spi-mem.c | 7 + include/spi-mem.h | 3 + 3 files changed, 451 insertions(+), 206 deletions(-)