Add dtsi file for i.MXRT1020.
Signed-off-by: Giulio Benetti giulio.benetti@benettiengineering.com --- arch/arm/dts/imxrt1020.dtsi | 133 ++++++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 arch/arm/dts/imxrt1020.dtsi
diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi new file mode 100644 index 0000000000..97f3cec9f3 --- /dev/null +++ b/arch/arm/dts/imxrt1020.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 + * Author(s): Giulio Benetti giulio.benetti@benettiengineering.com + */ + +#include "armv7-m.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/imxrt1020-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/memory/imxrt-sdram.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + mmc0 = &usdhc1; + serial0 = &lpuart1; + }; + + clocks { + u-boot,dm-spl; + ckil { + compatible = "fsl,imx-ckil", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + osc { + u-boot,dm-spl; + compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + soc { + u-boot,dm-spl; + + semc: semc@402f0000 { + u-boot,dm-spl; + compatible = "fsl,imxrt-semc"; + reg = <0x402f0000 0x4000>; + clocks = <&clks IMXRT1020_CLK_SEMC>; + pinctrl-0 = <&pinctrl_semc>; + pinctrl-names = "default"; + status = "okay"; + }; + + lpuart1: serial@40184000 { + compatible = "fsl,imxrt-lpuart"; + reg = <0x40184000 0x4000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMXRT1020_CLK_LPUART1>; + clock-names = "per"; + status = "disabled"; + }; + + iomuxc: iomuxc@401f8000 { + compatible = "fsl,imxrt-iomuxc"; + reg = <0x401f8000 0x4000>; + fsl,mux_mask = <0x7>; + }; + + clks: ccm@400fc000 { + u-boot,dm-spl; + compatible = "fsl,imxrt1020-ccm"; + reg = <0x400fc000 0x4000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + }; + + usdhc1: usdhc@402c0000 { + u-boot,dm-spl; + compatible = "fsl,imxrt-usdhc"; + reg = <0x402c0000 0x10000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMXRT1020_CLK_USDHC1>; + clock-names = "per"; + bus-width = <4>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + gpio1: gpio@401b8000 { + u-boot,dm-spl; + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x401b8000 0x4000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@401bc000 { + u-boot,dm-spl; + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x401bc000 0x4000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@401c0000 { + u-boot,dm-spl; + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x401c0000 0x4000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +};