Hi Stefan, On Wed, Jan 06, 2016 at 11:04:44PM -0800, Stefan Agner wrote:
On 2016-01-04 21:56, Peng Fan wrote:
From: Peng Fan peng.fan@nxp.com
In current design, if any peripheral was assigned to both A7 and M4, it will receive ipg_stop or ipg_wait when any of the 2 platforms enter low power mode. We will have a risk that, if A7 enter wait, M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait asserted same time. Also if M4 enters stop mode, A7 will have no chance to access the peripheral. There are 26 peripherals impacted by this IC issue:
s/impacted/affected
Will fix in V2.
SIM2(sim2/emvsim2) SIM1(sim1/emvsim1) UART1/UART2/UART3/UART4/UART5/UART6/UART7 SAI1/SAI2/SAI3 WDOG1/WDOG2/WDOG3/WDOG4 GPT1/GPT2/GPT3/GPT4 PWM1/PWM2/PWM3/PWM4 ENET1/ENET2 Software Workaround: The solution is set M4 to a different domain with A core.
Set the M4 core to a different domain using A core? Or merely the peripherals?
peripherals. Thanks pointing this.
So the peripherals are not shared by them. This way requires the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only. M4 image will set the M4 to domain 1 and set peripheral which it will use to domain 1.
Hm, what happens if the M4 image is not doing that? Would that causing problems?
If M4 A7 and all the peripherals are in one domain, if A7 runs into low power idle or other low mode, it will send out ipg_stop/wait signal, and m4 will not be able to access the peripherals. So need to assign peripherals to different domains for M4 and A7.
Thanks, Peng.
-- Stefan
This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for i.MX7D SABRESD board, and setup the 26 IP resources to domain 0.
Signed-off-by: Ye.Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com
arch/arm/cpu/armv7/mx7/soc.c | 64 +++++++++++++++++++++++++++++++++++++++++++ configs/mx7dsabresd_defconfig | 2 ++ 2 files changed, 66 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index 2121ff2..ede7d53 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -12,6 +12,8 @@ #include <asm/imx-common/boot_mode.h> #include <asm/imx-common/dma.h> #include <asm/imx-common/hab.h> +#include <asm/imx-common/rdc-sema.h> +#include <asm/arch/imx-rdc.h> #include <asm/arch/crm_regs.h> #include <dm.h> #include <imx_thermal.h> @@ -29,6 +31,65 @@ U_BOOT_DEVICE(imx7_thermal) = { }; #endif
+#ifdef CONFIG_IMX_RDC +/*
- In current design, if any peripheral was assigned to both A7 and M4,
- it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
- low power mode. So M4 sleep will cause some peripherals fail to work
- at A7 core side. At default, all resources are in domain 0 - 3.
- There are 26 peripherals impacted by this IC issue:
- SIM2(sim2/emvsim2)
- SIM1(sim1/emvsim1)
- UART1/UART2/UART3/UART4/UART5/UART6/UART7
- SAI1/SAI2/SAI3
- WDOG1/WDOG2/WDOG3/WDOG4
- GPT1/GPT2/GPT3/GPT4
- PWM1/PWM2/PWM3/PWM4
- ENET1/ENET2
- Software Workaround:
- Here we setup some resources to domain 0 where M4 codes will move
- the M4 out of this domain. Then M4 is not able to access them any longer.
- This is a workaround for ic issue. So the peripherals are not shared
- by them. This way requires the uboot implemented the RDC driver and
- set the 26 IPs above to domain 0 only. M4 code will assign resource
- to its own domain, if it want to use the resource.
- */
+static rdc_peri_cfg_t const resources[] = {
- (RDC_PER_SIM1 | RDC_DOMAIN(0)),
- (RDC_PER_SIM2 | RDC_DOMAIN(0)),
- (RDC_PER_UART1 | RDC_DOMAIN(0)),
- (RDC_PER_UART2 | RDC_DOMAIN(0)),
- (RDC_PER_UART3 | RDC_DOMAIN(0)),
- (RDC_PER_UART4 | RDC_DOMAIN(0)),
- (RDC_PER_UART5 | RDC_DOMAIN(0)),
- (RDC_PER_UART6 | RDC_DOMAIN(0)),
- (RDC_PER_UART7 | RDC_DOMAIN(0)),
- (RDC_PER_SAI1 | RDC_DOMAIN(0)),
- (RDC_PER_SAI2 | RDC_DOMAIN(0)),
- (RDC_PER_SAI3 | RDC_DOMAIN(0)),
- (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
- (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
- (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
- (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
- (RDC_PER_GPT1 | RDC_DOMAIN(0)),
- (RDC_PER_GPT2 | RDC_DOMAIN(0)),
- (RDC_PER_GPT3 | RDC_DOMAIN(0)),
- (RDC_PER_GPT4 | RDC_DOMAIN(0)),
- (RDC_PER_PWM1 | RDC_DOMAIN(0)),
- (RDC_PER_PWM2 | RDC_DOMAIN(0)),
- (RDC_PER_PWM3 | RDC_DOMAIN(0)),
- (RDC_PER_PWM4 | RDC_DOMAIN(0)),
- (RDC_PER_ENET1 | RDC_DOMAIN(0)),
- (RDC_PER_ENET2 | RDC_DOMAIN(0)),
+};
+static void isolate_resource(void) +{
- imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
+} +#endif
#if defined(CONFIG_SECURE_BOOT) struct imx_sec_config_fuse_t const imx_sec_config_fuse = { .bank = 1, @@ -163,6 +224,9 @@ int arch_cpu_init(void) mxs_dma_init(); #endif
- if (IS_ENABLED(CONFIG_IMX_RDC))
isolate_resource();- return 0;
}
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 420d13e..1d262c1 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y CONFIG_TARGET_MX7DSABRESD=y +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg,MX7D" # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_IMI is not set