Thanks Albert,
On 11/17/2014 11:21 PM, Albert ARIBAUD wrote:
Hello Vikas,
On Mon, 17 Nov 2014 17:30:25 -0800, Vikas Manocha vikas.manocha@st.com wrote:
stv0991 architecture support added. It contains the support for following blocks
- Timer
- uart
Signed-off-by: Vikas Manocha vikas.manocha@st.com
Changes in v4:
- added maintainers info
I don't see the MAINTAINERS file added here; it is in 4/4 which (unless I've missed requests to the opposite effect) should be merged with 1/4.
You are right, it is mentioned here but actually is in 4/4. I will merge 4/4 with 1/4.
Rgds, Vikas
- rebased to current master
Changes in v3:
- removed period from commit message
Changes in v2:
corrected files license to GPL-2.0+
replaced printf() usage with puts() for string print
arch/arm/Kconfig | 5 + arch/arm/cpu/armv7/stv0991/Makefile | 9 ++ arch/arm/cpu/armv7/stv0991/clock.c | 27 +++++ arch/arm/cpu/armv7/stv0991/lowlevel.S | 12 +++ arch/arm/cpu/armv7/stv0991/pinmux.c | 48 +++++++++ arch/arm/cpu/armv7/stv0991/reset.c | 26 +++++ arch/arm/cpu/armv7/stv0991/timer.c | 114 ++++++++++++++++++++ arch/arm/include/asm/arch-stv0991/hardware.h | 73 +++++++++++++ arch/arm/include/asm/arch-stv0991/stv0991_cgu.h | 80 ++++++++++++++ arch/arm/include/asm/arch-stv0991/stv0991_creg.h | 82 ++++++++++++++ arch/arm/include/asm/arch-stv0991/stv0991_defs.h | 16 +++ arch/arm/include/asm/arch-stv0991/stv0991_gpt.h | 43 ++++++++ arch/arm/include/asm/arch-stv0991/stv0991_periph.h | 43 ++++++++ arch/arm/include/asm/arch-stv0991/stv0991_wdru.h | 28 +++++ board/st/stv0991/Kconfig | 23 ++++ board/st/stv0991/Makefile | 8 ++ board/st/stv0991/stv0991.c | 54 ++++++++++ configs/stv0991_defconfig | 3 + include/configs/stv0991.h | 58 ++++++++++ 19 files changed, 752 insertions(+) create mode 100644 arch/arm/cpu/armv7/stv0991/Makefile create mode 100644 arch/arm/cpu/armv7/stv0991/clock.c create mode 100644 arch/arm/cpu/armv7/stv0991/lowlevel.S create mode 100644 arch/arm/cpu/armv7/stv0991/pinmux.c create mode 100644 arch/arm/cpu/armv7/stv0991/reset.c create mode 100644 arch/arm/cpu/armv7/stv0991/timer.c create mode 100644 arch/arm/include/asm/arch-stv0991/hardware.h create mode 100644 arch/arm/include/asm/arch-stv0991/stv0991_cgu.h create mode 100644 arch/arm/include/asm/arch-stv0991/stv0991_creg.h create mode 100644 arch/arm/include/asm/arch-stv0991/stv0991_defs.h create mode 100644 arch/arm/include/asm/arch-stv0991/stv0991_gpt.h create mode 100644 arch/arm/include/asm/arch-stv0991/stv0991_periph.h create mode 100644 arch/arm/include/asm/arch-stv0991/stv0991_wdru.h create mode 100644 board/st/stv0991/Kconfig create mode 100644 board/st/stv0991/Makefile create mode 100644 board/st/stv0991/stv0991.c create mode 100644 configs/stv0991_defconfig create mode 100644 include/configs/stv0991.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3955978..71faf5e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -339,6 +339,10 @@ config TARGET_SPEAR600 bool "Support spear600" select CPU_ARM926EJS
+config TARGET_STV0991
bool "Support stv0991"select CPU_V7- config TARGET_X600 bool "Support x600" select CPU_ARM926EJS
@@ -932,6 +936,7 @@ source "board/spear/spear600/Kconfig" source "board/spear/x600/Kconfig" source "board/st-ericsson/snowball/Kconfig" source "board/st-ericsson/u8500/Kconfig" +source "board/st/stv0991/Kconfig" source "board/sunxi/Kconfig" source "board/syteco/jadecpu/Kconfig" source "board/syteco/zmx25/Kconfig" diff --git a/arch/arm/cpu/armv7/stv0991/Makefile b/arch/arm/cpu/armv7/stv0991/Makefile new file mode 100644 index 0000000..95641d3 --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 +# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := timer.o clock.o pinmux.o reset.o +obj-y += lowlevel.o diff --git a/arch/arm/cpu/armv7/stv0991/clock.c b/arch/arm/cpu/armv7/stv0991/clock.c new file mode 100644 index 0000000..aca6aba --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/clock.c @@ -0,0 +1,27 @@ +/*
- (C) Copyright 2014
- Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/stv0991_cgu.h> +#include<asm/arch/stv0991_periph.h>
+static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);+void clock_setup(int peripheral) +{
switch (peripheral) {case UART_CLOCK_CFG:writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq);break;case ETH_CLOCK_CFG:break;default:break;}+} diff --git a/arch/arm/cpu/armv7/stv0991/lowlevel.S b/arch/arm/cpu/armv7/stv0991/lowlevel.S new file mode 100644 index 0000000..6dafba3 --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/lowlevel.S @@ -0,0 +1,12 @@ +/*
- (C) Copyright 2014 stmicroelectronics
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <config.h> +#include <linux/linkage.h>
+ENTRY(lowlevel_init)
mov pc, lr+ENDPROC(lowlevel_init) diff --git a/arch/arm/cpu/armv7/stv0991/pinmux.c b/arch/arm/cpu/armv7/stv0991/pinmux.c new file mode 100644 index 0000000..6d4414a --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/pinmux.c @@ -0,0 +1,48 @@ +/*
- (C) Copyright 2014
- Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <asm/io.h> +#include <asm/arch/stv0991_creg.h> +#include <asm/arch/stv0991_periph.h> +#include <asm/arch/hardware.h>
+static struct stv0991_creg *const stv0991_creg = \
(struct stv0991_creg *)CREG_BASE_ADDR;+int stv0991_pinmux_config(int peripheral) +{
switch (peripheral) {case UART_GPIOC_30_31:/* SSDA/SSCL pad muxing to UART Rx/Dx */writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) |CFG_GPIOC_31_UART_RX,&stv0991_creg->mux12);writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) |CFG_GPIOC_30_UART_TX,&stv0991_creg->mux12);/* SSDA/SSCL pad config to push pull*/writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) |CFG_GPIOC_31_MODE_PP,&stv0991_creg->cfg_pad6);writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) |CFG_GPIOC_30_MODE_HIGH,&stv0991_creg->cfg_pad6);break;case UART_GPIOB_16_17:/* ethernet rx_6/7 to UART Rx/Dx */writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) |CFG_GPIOB_17_UART_RX,&stv0991_creg->mux7);writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) |CFG_GPIOB_16_UART_TX,&stv0991_creg->mux7);break;default:break;}return 0;+} diff --git a/arch/arm/cpu/armv7/stv0991/reset.c b/arch/arm/cpu/armv7/stv0991/reset.c new file mode 100644 index 0000000..3384b32 --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/reset.c @@ -0,0 +1,26 @@ +/*
- (C) Copyright 2014
- Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/arch/stv0991_wdru.h> +void reset_cpu(ulong ignored) +{
puts("System is going to reboot ...\n");/** This 1 second delay will allow the above message* to be printed before reset*/udelay((1000 * 1000));/* Setting bit 1 of the WDRU unit will reset the SoC */writel(WDRU_RST_SYS, &stv0991_wd_ru_ptr->wdru_ctrl1);/* system will restart */while (1);+} diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c new file mode 100644 index 0000000..8654b8b --- /dev/null +++ b/arch/arm/cpu/armv7/stv0991/timer.c @@ -0,0 +1,114 @@ +/*
- (C) Copyright 2014
- Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/arch-stv0991/hardware.h> +#include <asm/arch-stv0991/stv0991_cgu.h> +#include <asm/arch-stv0991/stv0991_gpt.h>
+static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);+#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) +#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ)
+DECLARE_GLOBAL_DATA_PTR;
+#define timestamp gd->arch.tbl +#define lastdec gd->arch.lastinc
+int timer_init(void) +{
/* Timer1 clock configuration */writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq);writel(readl(&stv0991_cgu_regs->cgu_enable_2) |TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2);/* Stop the timer */writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc);/* Configure timer for auto-reload */writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD,&gpt1_regs_ptr->cr1);/* load value for free running */writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr);/* start timer */writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN,&gpt1_regs_ptr->cr1);/* Reset the timer */lastdec = READ_TIMER();timestamp = 0;return 0;+}
+/*
- timer without interrupts
- */
+ulong get_timer(ulong base) +{
return (get_timer_masked() / GPT_RESOLUTION) - base;+}
+void __udelay(unsigned long usec) +{
ulong tmo;ulong start = get_timer_masked();ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100);ulong rndoff;rndoff = (usec % 10) ? 1 : 0;/* tenudelcnt timer tick gives 10 microsecconds delay */tmo = ((usec / 10) + rndoff) * tenudelcnt;while ((ulong) (get_timer_masked() - start) < tmo);+}
+ulong get_timer_masked(void) +{
ulong now = READ_TIMER();if (now >= lastdec) {/* normal mode */timestamp += now - lastdec;} else {/* we have an overflow ... */timestamp += now + GPT_FREE_RUNNING - lastdec;}lastdec = now;return timestamp;+}
+void udelay_masked(unsigned long usec) +{
return udelay(usec);+}
+/*
- This function is derived from PowerPC code (read timebase as long long).
- On ARM it just returns the timer value.
- */
+unsigned long long get_ticks(void) +{
return get_timer(0);+}
+/*
- This function is derived from PowerPC code (timebase clock frequency).
- On ARM it returns the number of timer ticks per second.
- */
+ulong get_tbclk(void) +{
return CONFIG_STV0991_HZ;+} diff --git a/arch/arm/include/asm/arch-stv0991/hardware.h b/arch/arm/include/asm/arch-stv0991/hardware.h new file mode 100644 index 0000000..3f6bcaf --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/hardware.h @@ -0,0 +1,73 @@ +/*
- (C) Copyright 2014
- Vikas Manocha, STMicroelectronics, vikas.manocha@st.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H
+/* STV0991 */ +#define SRAM0_BASE_ADDR 0x00000000UL +#define SRAM1_BASE_ADDR 0x00068000UL +#define SRAM2_BASE_ADDR 0x000D0000UL +#define SRAM3_BASE_ADDR 0x00138000UL +#define CFS_SRAM0_BASE_ADDR 0x00198000UL +#define CFS_SRAM1_BASE_ADDR 0x001B8000UL +#define FAST_SRAM_BASE_ADDR 0x001D8000UL +#define FLASH_BASE_ADDR 0x40000000UL +#define PL310_BASE_ADDR 0x70000000UL +#define HSAXIM_BASE_ADDR 0x70100000UL +#define IMGSS_BASE_ADDR 0x70200000UL +#define ADC_BASE_ADDR 0x80000000UL +#define GPIOA_BASE_ADDR 0x80001000UL +#define GPIOB_BASE_ADDR 0x80002000UL +#define GPIOC_BASE_ADDR 0x80003000UL +#define HDM_BASE_ADDR 0x80004000UL +#define THSENS_BASE_ADDR 0x80200000UL +#define GPTIMER2_BASE_ADDR 0x80201000UL +#define GPTIMER1_BASE_ADDR 0x80202000UL +#define QSPI_BASE_ADDR 0x80203000UL +#define CGU_BASE_ADDR 0x80204000UL +#define CREG_BASE_ADDR 0x80205000UL +#define PEC_BASE_ADDR 0x80206000UL +#define WDRU_BASE_ADDR 0x80207000UL +#define BSEC_BASE_ADDR 0x80208000UL +#define DAP_ROM_BASE_ADDR 0x80210000UL +#define SOC_CTI_BASE_ADDR 0x80211000UL +#define TPIU_BASE_ADDR 0x80212000UL +#define TMC_ETF_BASE_ADDR 0x80213000UL +#define R4_ETM_BASE_ADDR 0x80214000UL +#define R4_CTI_BASE_ADDR 0x80215000UL +#define R4_DBG_BASE_ADDR 0x80216000UL +#define GMAC_BASE_ADDR 0x80300000UL +#define RNSS_BASE_ADDR 0x80302000UL +#define CRYP_BASE_ADDR 0x80303000UL +#define HASH_BASE_ADDR 0x80304000UL +#define GPDMA_BASE_ADDR 0x80305000UL +#define ISA_BASE_ADDR 0x8032A000UL +#define HCI_BASE_ADDR 0x80400000UL +#define I2C1_BASE_ADDR 0x80401000UL +#define I2C2_BASE_ADDR 0x80402000UL +#define SAI_BASE_ADDR 0x80403000UL +#define USI_BASE_ADDR 0x80404000UL +#define SPI1_BASE_ADDR 0x80405000UL +#define UART_BASE_ADDR 0x80406000UL +#define SPI2_BASE_ADDR 0x80500000UL +#define CAN_BASE_ADDR 0x80501000UL +#define USART1_BASE_ADDR 0x80502000UL +#define USART2_BASE_ADDR 0x80503000UL +#define USART3_BASE_ADDR 0x80504000UL +#define USART4_BASE_ADDR 0x80505000UL +#define USART5_BASE_ADDR 0x80506000UL +#define USART6_BASE_ADDR 0x80507000UL +#define SDI2_BASE_ADDR 0x80600000UL +#define SDI1_BASE_ADDR 0x80601000UL +#define VICA_BASE_ADDR 0x81000000UL +#define VICB_BASE_ADDR 0x81001000UL +#define STM_CHANNELS_BASE_ADDR 0x81100000UL +#define STM_BASE_ADDR 0x81110000UL +#define SROM_BASE_ADDR 0xFFFF0000UL
+#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h new file mode 100644 index 0000000..4926395 --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h @@ -0,0 +1,80 @@ +/*
- (C) Copyright 2014
- Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _STV0991_CGU_H +#define _STV0991_CGU_H
+struct stv0991_cgu_regs {
u32 cpu_freq; /* offset 0x0 */u32 icn2_freq; /* offset 0x4 */u32 dma_freq; /* offset 0x8 */u32 isp_freq; /* offset 0xc */u32 h264_freq; /* offset 0x10 */u32 osif_freq; /* offset 0x14 */u32 ren_freq; /* offset 0x18 */u32 tim_freq; /* offset 0x1c */u32 sai_freq; /* offset 0x20 */u32 eth_freq; /* offset 0x24 */u32 i2c_freq; /* offset 0x28 */u32 spi_freq; /* offset 0x2c */u32 uart_freq; /* offset 0x30 */u32 qspi_freq; /* offset 0x34 */u32 sdio_freq; /* offset 0x38 */u32 usi_freq; /* offset 0x3c */u32 can_line_freq; /* offset 0x40 */u32 debug_freq; /* offset 0x44 */u32 trace_freq; /* offset 0x48 */u32 stm_freq; /* offset 0x4c */u32 eth_ctrl; /* offset 0x50 */u32 reserved[3]; /* offset 0x54 */u32 osc_ctrl; /* offset 0x60 */u32 pll1_ctrl; /* offset 0x64 */u32 pll1_freq; /* offset 0x68 */u32 pll1_fract; /* offset 0x6c */u32 pll1_spread; /* offset 0x70 */u32 pll1_status; /* offset 0x74 */u32 pll2_ctrl; /* offset 0x78 */u32 pll2_freq; /* offset 0x7c */u32 pll2_fract; /* offset 0x80 */u32 pll2_spread; /* offset 0x84 */u32 pll2_status; /* offset 0x88 */u32 cgu_enable_1; /* offset 0x8c */u32 cgu_enable_2; /* offset 0x90 */u32 cgu_isp_pulse; /* offset 0x94 */u32 cgu_h264_pulse; /* offset 0x98 */u32 cgu_osif_pulse; /* offset 0x9c */u32 cgu_ren_pulse; /* offset 0xa0 */+};
+/* CGU Timer */ +#define CLK_TMR_OSC 0 +#define CLK_TMR_MCLK 1 +#define CLK_TMR_PLL1 2 +#define CLK_TMR_PLL2 3 +#define MDIV_SHIFT_TMR 3 +#define DIV_SHIFT_TMR 6
+#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \
| 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK)+/* Clock Enable/Disable */
+#define TIMER1_CLK_EN (1 << 15)
+/* CGU Uart config */ +#define CLK_UART_MCLK 0 +#define CLK_UART_PLL1 1 +#define CLK_UART_PLL2 2
+#define MDIV_SHIFT_UART 3 +#define DIV_SHIFT_UART 6
+#define UART_CLK_CFG (4 << DIV_SHIFT_UART \
| 1 << MDIV_SHIFT_UART | CLK_UART_MCLK)+#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h new file mode 100644 index 0000000..045dbfe --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h @@ -0,0 +1,82 @@ +/*
- (C) Copyright 2014
- Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _STV0991_CREG_H +#define _STV0991_CREG_H
+struct stv0991_creg {
u32 version; /* offset 0x0 */u32 hdpctl; /* offset 0x4 */u32 hdpval; /* offset 0x8 */u32 hdpgposet; /* offset 0xc */u32 hdpgpoclr; /* offset 0x10 */u32 hdpgpoval; /* offset 0x14 */u32 stm_mux; /* offset 0x18 */u32 sysctrl_1; /* offset 0x1c */u32 sysctrl_2; /* offset 0x20 */u32 sysctrl_3; /* offset 0x24 */u32 sysctrl_4; /* offset 0x28 */u32 reserved_1[0x35]; /* offset 0x2C-0xFC */u32 mux1; /* offset 0x100 */u32 mux2; /* offset 0x104 */u32 mux3; /* offset 0x108 */u32 mux4; /* offset 0x10c */u32 mux5; /* offset 0x110 */u32 mux6; /* offset 0x114 */u32 mux7; /* offset 0x118 */u32 mux8; /* offset 0x11c */u32 mux9; /* offset 0x120 */u32 mux10; /* offset 0x124 */u32 mux11; /* offset 0x128 */u32 mux12; /* offset 0x12c */u32 mux13; /* offset 0x130 */u32 reserved_2[0x33]; /* offset 0x134-0x1FC */u32 cfg_pad1; /* offset 0x200 */u32 cfg_pad2; /* offset 0x204 */u32 cfg_pad3; /* offset 0x208 */u32 cfg_pad4; /* offset 0x20c */u32 cfg_pad5; /* offset 0x210 */u32 cfg_pad6; /* offset 0x214 */u32 cfg_pad7; /* offset 0x218 */u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */u32 vdd_pad1; /* offset 0x300 */u32 vdd_pad2; /* offset 0x304 */u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */u32 vdd_comp1; /* offset 0x400 */+};
+/* CREG MUX 12 register */ +#define GPIOC_30_MUX_SHIFT 24 +#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT) +#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT)
+#define GPIOC_31_MUX_SHIFT 28 +#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT) +#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT)
+/* CREG MUX 7 register */ +#define GPIOB_16_MUX_SHIFT 0 +#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT) +#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT)
+#define GPIOB_17_MUX_SHIFT 4 +#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT) +#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT)
+/* CREG CFG_PAD6 register */
+#define GPIOC_31_MODE_SHIFT 30 +#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT) +#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT) +#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT)
+#define GPIOC_30_MODE_SHIFT 28 +#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT) +#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT) +#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT)
+#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h new file mode 100644 index 0000000..1151378 --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h @@ -0,0 +1,16 @@ +/*
- (C) Copyright 2014
- Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __STV0991_DEFS_H__ +#define __STV0991_DEFS_H__ +#include <asm/arch/stv0991_periph.h>
+extern int stv0991_pinmux_config(enum periph_id); +extern int clock_setup(enum periph_clock);
+#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h new file mode 100644 index 0000000..abd7257 --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h @@ -0,0 +1,43 @@ +/*
- (C) Copyright 2014
- Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _STV0991_GPT_H +#define _STV0991_GPT_H
+#include <asm/arch-stv0991/hardware.h>
+struct gpt_regs {
u32 cr1;u32 cr2;u32 reserved_1;u32 dier; /* dma_int_en */u32 sr; /* status reg */u32 egr; /* event gen */u32 reserved_2[3]; /* offset 0x18--0x20*/u32 cnt;u32 psc;u32 arr;+};
+struct gpt_regs *const gpt1_regs_ptr =
(struct gpt_regs *) GPTIMER1_BASE_ADDR;+/* Timer control1 register */ +#define GPT_CR1_CEN 0x0001 +#define GPT_MODE_AUTO_RELOAD (1 << 7)
+/* Timer prescalar reg */ +#define GPT_PRESCALER_128 0x128
+/* Auto reload register for free running config */ +#define GPT_FREE_RUNNING 0xFFFF
+/* Timer, HZ specific defines */ +#define CONFIG_STV0991_HZ 1000 +#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128
+#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h new file mode 100644 index 0000000..f723771 --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h @@ -0,0 +1,43 @@ +/*
- (C) Copyright 2014
- Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H
+/*
- Peripherals required for pinmux configuration. List will
- grow with support for more devices getting added.
- Numbering based on interrupt table.
- */
+enum periph_id {
UART_GPIOC_30_31 = 0,UART_GPIOB_16_17,PERIPH_ID_I2C0,PERIPH_ID_I2C1,PERIPH_ID_I2C2,PERIPH_ID_I2C3,PERIPH_ID_I2C4,PERIPH_ID_I2C5,PERIPH_ID_I2C6,PERIPH_ID_I2C7,PERIPH_ID_SPI0,PERIPH_ID_SPI1,PERIPH_ID_SPI2,PERIPH_ID_SDMMC0,PERIPH_ID_SDMMC1,PERIPH_ID_SDMMC2,PERIPH_ID_SDMMC3,PERIPH_ID_I2S1,+};
+enum periph_clock {
UART_CLOCK_CFG = 0,ETH_CLOCK_CFG,+};
+#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h b/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h new file mode 100644 index 0000000..7e555a2 --- /dev/null +++ b/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h @@ -0,0 +1,28 @@ +/*
- (C) Copyright 2014
- Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _STV0991_WD_RST_H +#define _STV0991_WD_RST_H +#include <asm/arch-stv0991/hardware.h>
+struct stv0991_wd_ru {
u32 wdru_config;u32 wdru_ctrl1;u32 wdru_ctrl2;u32 wdru_tim;u32 wdru_count;u32 wdru_stat;u32 wdru_wrlock;+};
+struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \
(struct stv0991_wd_ru *)WDRU_BASE_ADDR;+/* Watchdog control register */ +#define WDRU_RST_SYS 0x1
+#endif diff --git a/board/st/stv0991/Kconfig b/board/st/stv0991/Kconfig new file mode 100644 index 0000000..8bda349 --- /dev/null +++ b/board/st/stv0991/Kconfig @@ -0,0 +1,23 @@ +if TARGET_STV0991
+config SYS_CPU
stringdefault "armv7"+config SYS_BOARD
stringdefault "stv0991"+config SYS_VENDOR
stringdefault "st"+config SYS_SOC
stringdefault "stv0991"+config SYS_CONFIG_NAME
stringdefault "stv0991"+endif diff --git a/board/st/stv0991/Makefile b/board/st/stv0991/Makefile new file mode 100644 index 0000000..fb5169a --- /dev/null +++ b/board/st/stv0991/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 +# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := stv0991.o diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c new file mode 100644 index 0000000..bdeb53c --- /dev/null +++ b/board/st/stv0991/stv0991.c @@ -0,0 +1,54 @@ +/*
- (C) Copyright 2014
- Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <miiphy.h> +#include <asm/arch/stv0991_periph.h> +#include <asm/arch/stv0991_defs.h>
+DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress(int progress) +{
printf("%i\n", progress);+} +#endif
+/*
- Miscellaneous platform dependent initialisations
- */
+int board_init(void) +{
return 0;+}
+int board_uart_init(void) +{
stv0991_pinmux_config(UART_GPIOC_30_31);clock_setup(UART_CLOCK_CFG);return 0;+} +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{
board_uart_init();return 0;+} +#endif
+int dram_init(void) +{
gd->ram_size = PHYS_SDRAM_1_SIZE;return 0;+}
+void dram_init_banksize(void) +{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;+} diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig new file mode 100644 index 0000000..a05e991 --- /dev/null +++ b/configs/stv0991_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="stv0991" +CONFIG_ARM=y +CONFIG_TARGET_STV0991=y diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h new file mode 100644 index 0000000..864a63f --- /dev/null +++ b/include/configs/stv0991.h @@ -0,0 +1,58 @@ +/*
- (C) Copyright 2014
- Vikas Manocha, STMicroelectronics, vikas.manocha@st.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_STV0991_H +#define __CONFIG_STV0991_H
+#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SYS_CORTEX_R4
+#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_NO_FLASH
+/* ram memory-related information */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define PHYS_SDRAM_1_SIZE 0x00198000
+#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR \
(PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)+#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024)
+/* serial port (PL011) configuration */ +#define CONFIG_SYS_SERIAL0 0x80406000 +#define CONFIG_PL011_SERIAL +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} +#define CONFIG_PL011_CLOCK (2700 * 1000)
+/* user interface */ +#define CONFIG_SYS_PROMPT "STV0991> " +#define CONFIG_SYS_CBSIZE 256/* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+sizeof(CONFIG_SYS_PROMPT) + 16)+/* MISC */ +#define CONFIG_SYS_LOAD_ADDR 0x00000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 +#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)+/* U-boot Load Address */ +#define CONFIG_SYS_TEXT_BASE 0x00010000 +#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)+#endif /* __CONFIG_H */
1.7.9.5
Amicalement,
Albert. .