On Wednesday 09 July 2008, Grant Erickson wrote:
While the PowerPC 405EX(r) shares in common the AMCC/IBM DDR2 SDRAM controller core also used in the 440SP, 440SPe, 460EX, and 460GT, in the 405EX(r), SDRAM_MCSTAT has a different DCR value.
Its present value on the 405EX(r) causes a read back of 0xFFFFFFFF which causes SDRAM initialization to periodically fail since it can prematurely indicate SDRAM ready status.
Signed-off-by: Grant Erickson gerickson@nuovations.com
Applied to "next" branch in u-boot-ppc4xx repository. Thanks.
Best regards, Stefan
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