Re: [U-Boot] [PATCH v1] arm: imx: Add support for GE Bx50v3 boards

On 01/28/2016 10:12 PM, Peng Fan wrote:

Hi Akshay,

CC i.MX maintainer Stefano for you.

On Wed, Jan 27, 2016 at 05:53:47PM -0500, Akshay Bhat wrote:

...

Add support for GE B450v3, B650v3 and B850v3 boards. The boards are based on Advantech BA16 module which has a imx6 processor.

Which imx6 processor?

imx6d, updated the commit log in v2 patch.

...

The boards support:

• FEC Ethernet
• USB Ports
• SDHC and MMC boot
• SPI NOR
• LVDS and HDMI display

Basic information about the module:

• Module manufacturer: Advantech
• CPU: Freescale ARM Cortex-A9 i.MX6
• SPECS: Up to 2GB Onboard DDR3 Memory; Up to 16GB Onboard eMMC NAND Flash Supports OpenGL ES 2.0 and OpenVG 1.1 HDMI, 24-bit LVDS 1x UART, 2x I2C, 8x GPIO, 4x Host USB 2.0 port, 1x USB OTG port, 1x micro SD (SDHC),1x SDIO, 1x SATA II, 1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2

Signed-off-by: Akshay Bhat akshay.bhat@timesys.com

arch/arm/cpu/armv7/mx6/Kconfig | 10 + board/ge/bx50v3/Kconfig | 15 ++ board/ge/bx50v3/MAINTAINERS | 8 + board/ge/bx50v3/Makefile | 8 + board/ge/bx50v3/bx50v3.c | 534 +++++++++++++++++++++++++++++++++++++++++ board/ge/bx50v3/bx50v3.cfg | 151 ++++++++++++ configs/ge_b450v3_defconfig | 9 + configs/ge_b650v3_defconfig | 9 + configs/ge_b850v3_defconfig | 9 + include/configs/ge_bx50v3.h | 374 +++++++++++++++++++++++++++++ 10 files changed, 1127 insertions(+) create mode 100644 board/ge/bx50v3/Kconfig create mode 100644 board/ge/bx50v3/MAINTAINERS create mode 100644 board/ge/bx50v3/Makefile create mode 100644 board/ge/bx50v3/bx50v3.c create mode 100644 board/ge/bx50v3/bx50v3.cfg create mode 100644 configs/ge_b450v3_defconfig create mode 100644 configs/ge_b650v3_defconfig create mode 100644 configs/ge_b850v3_defconfig create mode 100644 include/configs/ge_bx50v3.h

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 8489182..c4e89f1 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -60,6 +60,15 @@ config TARGET_CM_FX6 config TARGET_EMBESTMX6BOARDS bool "embestmx6boards"

+config TARGET_GE_B450V3

• bool "General Electric B450v3"

+config TARGET_GE_B650V3

• bool "General Electric B650v3"

+config TARGET_GE_B850V3

• bool "General Electric B850v3"

config TARGET_GW_VENTANA bool "gw_ventana" select SUPPORT_SPL @@ -153,6 +162,7 @@ endchoice config SYS_SOC default "mx6"

+source "board/ge/bx50v3/Kconfig" source "board/aristainetos/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/barco/platinum/Kconfig" diff --git a/board/ge/bx50v3/Kconfig b/board/ge/bx50v3/Kconfig new file mode 100644 index 0000000..2c4a689 --- /dev/null +++ b/board/ge/bx50v3/Kconfig @@ -0,0 +1,15 @@ +if TARGET_GE_B450V3 || TARGET_GE_B650V3 || TARGET_GE_B850V3

+config SYS_BOARD

• default "bx50v3"

+config SYS_VENDOR

• default "ge"

+config SYS_SOC

• default "mx6"

+config SYS_CONFIG_NAME

• default "ge_bx50v3"

+endif diff --git a/board/ge/bx50v3/MAINTAINERS b/board/ge/bx50v3/MAINTAINERS new file mode 100644 index 0000000..8e60791 --- /dev/null +++ b/board/ge/bx50v3/MAINTAINERS @@ -0,0 +1,8 @@ +GE_BX50V3 BOARD +M: Martin Donnelly martin.donnelly@ge.com +S: Maintained +F: board/ge/bx50v3/ +F: include/configs/ge_bx50v3.h +F: configs/ge_b450v3_defconfig +F: configs/ge_b650v3_defconfig +F: configs/ge_b850v3_defconfig diff --git a/board/ge/bx50v3/Makefile b/board/ge/bx50v3/Makefile new file mode 100644 index 0000000..bcd149f --- /dev/null +++ b/board/ge/bx50v3/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2015 Timesys Corporation +# Copyright 2015 General Electric Company +# +# SPDX-License-Identifier: GPL-2.0+ +#

+obj-y := bx50v3.o diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c new file mode 100644 index 0000000..42035be --- /dev/null +++ b/board/ge/bx50v3/bx50v3.c @@ -0,0 +1,534 @@ +/*

• • Copyright 2015 Timesys Corporation
• • Copyright 2015 General Electric Company
• • Copyright 2012 Freescale Semiconductor, Inc.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/video.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +DECLARE_GLOBAL_DATA_PTR;

+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

• PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
• PAD_CTL_SRE_FAST | PAD_CTL_HYS)

+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \

• PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
• PAD_CTL_SRE_FAST | PAD_CTL_HYS)

+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \

• PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)

+#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \

• PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)

+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \

• PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)

+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \

•       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  

+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

• PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
• PAD_CTL_ODE | PAD_CTL_SRE_FAST)

+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)

+int dram_init(void) +{

• gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
• return 0;

+}

+iomux_v3_cfg_t const uart3_pads[] = {

Use static.

Fixed

...

• MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
• MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
• MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
• MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

+};

+iomux_v3_cfg_t const uart4_pads[] = {

Ditto. Also the following iomux definitions.

Fixed

...

• MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
• MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

+};

+iomux_v3_cfg_t const enet_pads[] = {

• MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
• MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
• MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
• MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
• MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
• MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
• MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
• MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
• /* AR8033 PHY Reset */
• MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),

+};

+static void setup_iomux_enet(void) +{

• imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
• /* Reset AR8033 PHY */
• gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
• udelay(500);
• gpio_set_value(IMX_GPIO_NR(1, 28), 1);

+}

+iomux_v3_cfg_t const usdhc2_pads[] = {

• MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),

+};

+iomux_v3_cfg_t const usdhc3_pads[] = {

• MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

+};

+iomux_v3_cfg_t const usdhc4_pads[] = {

• MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
• MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),

+};

+iomux_v3_cfg_t const ecspi1_pads[] = {

• MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
• MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
• MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
• MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),

+};

+static struct i2c_pads_info i2c_pad_info1 = {

• .scl = {

• .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
  

• .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
  

• .gp = IMX_GPIO_NR(5, 27)
  

• },
• .sda = {

• .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
  

• .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
  

• .gp = IMX_GPIO_NR(5, 26)
  

• }

+};

+static struct i2c_pads_info i2c_pad_info2 = {

• .scl = {

• .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
  

• .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
  

• .gp = IMX_GPIO_NR(4, 12)
  

• },
• .sda = {

• .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
  

• .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
  

• .gp = IMX_GPIO_NR(4, 13)
  

• }

+};

+static struct i2c_pads_info i2c_pad_info3 = {

• .scl = {

• .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
  

• .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
  

• .gp = IMX_GPIO_NR(1, 3)
  

• },
• .sda = {

• .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
  

• .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
  

• .gp = IMX_GPIO_NR(1, 6)
  

• }

+};

+#ifdef CONFIG_MXC_SPI +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{

• return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;

+}

+static void setup_spi(void) +{

• imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));

+} +#endif

+iomux_v3_cfg_t const pcie_pads[] = {

• MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
• MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),

+};

+static void setup_pcie(void) +{

• imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));

+}

+static void setup_iomux_uart(void) +{

• imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
• imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));

+}

+#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[3] = {

• {USDHC2_BASE_ADDR},
• {USDHC3_BASE_ADDR},
• {USDHC4_BASE_ADDR},

+};

+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) +#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)

+int board_mmc_getcd(struct mmc *mmc) +{

• struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
• int ret = 0;
• switch (cfg->esdhc_base) {
• case USDHC2_BASE_ADDR:

• ret = !gpio_get_value(USDHC2_CD_GPIO);
  

• break;
  

• case USDHC3_BASE_ADDR:

• ret = 1; /* eMMC/uSDHC4 is always present */
  

uSDHC4->uSDHC3?

Updated the comment.

...

• break;
  

• case USDHC4_BASE_ADDR:

• ret = !gpio_get_value(USDHC4_CD_GPIO);
  

• break;
  

• }
• return ret;

+}

+int board_mmc_init(bd_t *bis) +{

• int ret;
• int i;
• for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {

• switch (i) {
  

• case 0:
  

• 	imx_iomux_v3_setup_multiple_pads(
  

• 		usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  

• 	gpio_direction_input(USDHC2_CD_GPIO);
  

• 	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  

• 	break;
  

• case 1:
  

• 	imx_iomux_v3_setup_multiple_pads(
  

• 		usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  

• 	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  

• 	break;
  

• case 2:
  

• 	imx_iomux_v3_setup_multiple_pads(
  

• 		usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  

• 	gpio_direction_input(USDHC4_CD_GPIO);
  

• 	usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  

• 	break;
  

• default:
  

• 	printf("Warning: you configured more USDHC controllers\n"
  

• 	       "(%d) then supported by the board (%d)\n",
  

• 	       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
  

• 	return -EINVAL;
  

• }
  

• ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  

• if (ret)
  

• 	return ret;
  

• }
• return 0;

+} +#endif

+int mx6_rgmii_rework(struct phy_device *phydev)

static

Fixed

...

+{

• /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
• /* set device address 0x7 */
• phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
• /* offset 0x8016: CLK_25M Clock Select */
• phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
• /* enable register write, no post increment, address 0x7 */
• phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
• /* set to 125 MHz from local PLL source */
• phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
• /* rgmii tx clock delay enable */
• /* set debug port address: SerDes Test and System Mode Control */
• phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
• /* enable rgmii tx clock delay */
• phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
• return 0;

+}

+int board_phy_config(struct phy_device *phydev) +{

• mx6_rgmii_rework(phydev);
• if (phydev->drv->config)

• phydev->drv->config(phydev);
  

• return 0;

+}

+#if defined(CONFIG_VIDEO_IPUV3) +static iomux_v3_cfg_t const backlight_pads[] = {

• /* Power for LVDS Display */
• MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),

+#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)

• /* Backlight enable for LVDS display */
• MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),

+#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0) +};

+static void do_enable_hdmi(struct display_info_t const *dev) +{

• imx_enable_hdmi_phy();

+}

+int board_cfb_skip(void) +{

• gpio_direction_output(LVDS_POWER_GP, 1);
• return 0;

+}

+static int detect_baseboard(struct display_info_t const *dev) +{ +#if (defined CONFIG_TARGET_GE_B450V3 || defined CONFIG_TARGET_GE_B650V3)

     if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) || IS_ENABLED(CONFIG_TARGET_GE_B650V3))
return 1;

return 0;

Thanks for pointing this out, looks much cleaner this way.

...

• return 1;

+#else

• return 0;

+#endif +}

+struct display_info_t const displays[] = {{

• .bus = -1,
• .addr = -1,
• .pixfmt = IPU_PIX_FMT_RGB24,
• .detect = detect_baseboard,
• .enable = NULL,
• .mode = {

• .name           = "G121X1-L03",
  

• .refresh        = 60,
  

• .xres           = 1024,
  

• .yres           = 768,
  

• .pixclock       = 15385,
  

• .left_margin    = 20,
  

• .right_margin   = 300,
  

• .upper_margin   = 30,
  

• .lower_margin   = 8,
  

• .hsync_len      = 1,
  

• .vsync_len      = 1,
  

• .sync           = FB_SYNC_EXT,
  

• .vmode          = FB_VMODE_NONINTERLACED
  

+} }, {

• .bus = -1,
• .addr = 3,
• .pixfmt = IPU_PIX_FMT_RGB24,
• .detect = detect_hdmi,
• .enable = do_enable_hdmi,
• .mode = {

• .name           = "HDMI",
  

• .refresh        = 60,
  

• .xres           = 1024,
  

• .yres           = 768,
  

• .pixclock       = 15385,
  

• .left_margin    = 220,
  

• .right_margin   = 40,
  

• .upper_margin   = 21,
  

• .lower_margin   = 7,
  

• .hsync_len      = 60,
  

• .vsync_len      = 10,
  

• .sync           = FB_SYNC_EXT,
  

• .vmode          = FB_VMODE_NONINTERLACED
  

+} } }; +size_t display_count = ARRAY_SIZE(displays);

+static void setup_display(void) +{

• struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
• struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
• int reg;
• enable_ipu_clock();
• imx_setup_hdmi();
• reg = readl(&mxc_ccm->CCGR3);
• reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
• writel(reg, &mxc_ccm->CCGR3);
• reg = readl(&mxc_ccm->cs2cdr);
• reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |

•  MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  

• reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |

•       (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  

• writel(reg, &mxc_ccm->cs2cdr);
• reg = readl(&mxc_ccm->cscmr2);
• reg |= (MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
• writel(reg, &mxc_ccm->cscmr2);
• reg = readl(&mxc_ccm->chsccdr);
• reg |= (CHSCCDR_CLK_SEL_LDB_DI0

• << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  

• writel(reg, &mxc_ccm->chsccdr);
• reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES

•     | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  

•     | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  

•     | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  

•     | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
  

•     | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  

•     | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
  

•     | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
  

•     | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  

• writel(reg, &iomux->gpr[2]);
• reg = readl(&iomux->gpr[3]);
• reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |

•        IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
  

•        IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  

•    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  

•       << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
  

•    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  

•       << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
  

• writel(reg, &iomux->gpr[3]);
• /* backlights off until needed */
• imx_iomux_v3_setup_multiple_pads(backlight_pads,

• 			 ARRAY_SIZE(backlight_pads));
  

• gpio_direction_input(LVDS_POWER_GP);
• gpio_direction_input(LVDS_BACKLIGHT_GP);

+} +#endif /* CONFIG_VIDEO_IPUV3 */

+/*

• • Do not overwrite the console
• • Use always serial for U-Boot console
• */

+int overwrite_console(void) +{

• return 1;

+}

+int board_eth_init(bd_t *bis) +{

• setup_iomux_enet();
• setup_pcie();
• return cpu_eth_init(bis);

+}

+iomux_v3_cfg_t const misc_pads[] = {

• MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),

+}; +#define SUS_S3_OUT IMX_GPIO_NR(4, 11) +#define WIFI_EN IMX_GPIO_NR(6, 14)

+int board_early_init_f(void) +{

• imx_iomux_v3_setup_multiple_pads(misc_pads,

• 			 ARRAY_SIZE(misc_pads));
  

• gpio_direction_output(SUS_S3_OUT, 1);
• gpio_direction_output(WIFI_EN, 1);

Move the upper two line to board_init.

Fixed

...

• setup_iomux_uart();

+#if defined(CONFIG_VIDEO_IPUV3)

• setup_display();

+#endif

Move to board_init.

Fixed

...

• return 0;

+}

+int board_init(void) +{

• /* address of boot parameters */
• gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

+#ifdef CONFIG_MXC_SPI

• setup_spi();

+#endif

• setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
• setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
• setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
• return 0;

+}

+#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = {

• /* 4 bit bus width */
• {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
• {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
• /* 8 bit bus width */
• {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},

I guess 0x38 should be changed to 0x58?

We do not load u-boot from emmc, so removing the same.

...

• {NULL, 0},

+}; +#endif

+int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE

• add_board_boot_modes(board_boot_modes);

+#endif

• /* We need at least 200ms between power on and backlight on

• * as per specifications from CHI MEI */
  

• mdelay(250);
• /* Backlight Power */
• gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
• return 0;

+}

+int checkboard(void) +{

• printf("BOARD: %s\n", CONFIG_BOARD_NAME);
• return 0;

+} diff --git a/board/ge/bx50v3/bx50v3.cfg b/board/ge/bx50v3/bx50v3.cfg new file mode 100644 index 0000000..de88769 --- /dev/null +++ b/board/ge/bx50v3/bx50v3.cfg @@ -0,0 +1,151 @@ +/*

• • Copyright 2015 Timesys Corporation.
• • Copyright 2015 General Electric Company
• • SPDX-License-Identifier: GPL-2.0+
• • Refer doc/README.imximage for more details about how-to configure
• • and create imximage boot image
• • The syntax is taken as close as possible with the kwbimage
• */

+IMAGE_VERSION 2 +BOOT_FROM sd

+#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h"

+/* DDR IO */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030

+/* Calibrations */ +/* ZQ */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 +/* write leveling */ +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F +/* Read DQS Gating calibration */ +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x45380544 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x05280530 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4530053C +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0530050C +/* Read calibration */ +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x36303032 +DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38363042 +/* Write calibration */ +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A3A423E +DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A38483E +/* read data bit delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333

+/* Complete calibration by forced measurment */ +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800

+/* MMDC init */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDCFG0, 0x8A8F79A4 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538E64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 +DATA 4, MX6_MMDC_P0_MDOR, 0x008F1023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +DATA 4, MX6_MMDC_P0_MDCTL, 0x841a0000

+/* Initialize Micron MT41J128M */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803a +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b +DATA 4, MX6_MMDC_P0_MDSCR, 0x00408031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00408039 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 +DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000

+/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF

+/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F

+/*

• • Setup CCM_CCOSR register as follows:
• • cko1_en 1 --> CKO1 enabled
• • cko1_div 111 --> divide by 8
• • cko1_sel 1011 --> ahb_clk_root
• • This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
• */

+DATA 4, CCM_CCOSR, 0x000000fb diff --git a/configs/ge_b450v3_defconfig b/configs/ge_b450v3_defconfig new file mode 100644 index 0000000..21c6280 --- /dev/null +++ b/configs/ge_b450v3_defconfig @@ -0,0 +1,9 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_GE_B450V3=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/bx50v3/bx50v3.cfg" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/ge_b650v3_defconfig b/configs/ge_b650v3_defconfig new file mode 100644 index 0000000..6b4d1af --- /dev/null +++ b/configs/ge_b650v3_defconfig @@ -0,0 +1,9 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_GE_B650V3=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/bx50v3/bx50v3.cfg" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/ge_b850v3_defconfig b/configs/ge_b850v3_defconfig new file mode 100644 index 0000000..99bb98b --- /dev/null +++ b/configs/ge_b850v3_defconfig @@ -0,0 +1,9 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_GE_B850V3=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ge/bx50v3/bx50v3.cfg"

I think you may need to define MX6Q/MX6DL/xx in EXTRA_OPTIONS. Or you using select MX6x in you Kconfig in arch/arm/cpu/armv7/mx6/Kconfig.

Good catch it was currently defined in ge_bx50v3.h, moved it to Kconfig and also got rid of CONFIG_SYS_EXTRA_OPTIONS since it is deprecated.

...

+# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h new file mode 100644 index 0000000..299086d --- /dev/null +++ b/include/configs/ge_bx50v3.h @@ -0,0 +1,374 @@ +/*

• • Copyright (C) 2015 Timesys Corporation
• • Copyright (C) 2015 General Electric Company
• • Copyright (C) 2014 Advantech
• • Copyright (C) 2012 Freescale Semiconductor, Inc.
• • Configuration settings for the GE MX6Q Bx50v3 boards.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __GE_BX50V3_CONFIG_H +#define __GE_BX50V3_CONFIG_H

+#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h>

+#if defined(CONFIG_TARGET_GE_B450V3) +#define CONFIG_BOARD_NAME "General Electric B450v3" +#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b450v3.dtb" +#elif defined(CONFIG_TARGET_GE_B650V3) +#define CONFIG_BOARD_NAME "General Electric B650v3" +#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b650v3.dtb" +#elif defined(CONFIG_TARGET_GE_B850V3) +#define CONFIG_BOARD_NAME "General Electric B850v3" +#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b850v3.dtb" +#else +#define CONFIG_BOARD_NAME "General Electric BA16 Generic" +#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-ba16.dtb" +#endif

+#define CONFIG_MXC_UART_BASE UART3_BASE +#define CONFIG_CONSOLE_DEV "ttymxc2"

+#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)

+#define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_MX6Q

+#define CONFIG_BOOTDELAY 1

+#include "mx6_common.h" +#include <linux/sizes.h>

+#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO

+#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)

+#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT

+#define CONFIG_MXC_GPIO +#define CONFIG_MXC_UART

+#define CONFIG_CMD_FUSE +#define CONFIG_MXC_OCOTP

+/* SATA Configs */ +#define CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA

+/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION

+/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP

+#define CONFIG_CI_UDC +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 +#define CONFIG_G_DNL_MANUFACTURER "Advantech"

+/* Networking Configs */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 4 +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS

+/* Serial Flash */ +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif

+/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200

+/* Command definition */ +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_BOOTZ +#undef CONFIG_CMD_IMLS

+#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000

+#define CONFIG_EXTRA_ENV_SETTINGS \

• "script=boot.scr\0" \
• "image=/boot/uImage\0" \
• "uboot=u-boot.imx\0" \
• "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \

You can take include/configs/mx6sabre_common.h and board/freescale/mx6sabresd/mx6sabresd.c for reference to runtime setting env.

Thanks for pointing out this option. If we implement a mechanism to determine the board type in runtime, then this would be very useful. Until then this might not buy us much.

...

• "fdt_addr=0x18000000\0" \
• "boot_fdt=yes\0" \
• "ip_dyn=yes\0" \
• "console=" CONFIG_CONSOLE_DEV "\0" \
• "fdt_high=0xffffffff\0" \
• "initrd_high=0xffffffff\0" \
• "sddev=0\0" \
• "emmcdev=1\0" \
• "partnum=1\0" \
• "update_sd_firmware=" \

• "if test ${ip_dyn} = yes; then " \
  

• 	"setenv get_cmd dhcp; " \
  

• "else " \
  

• 	"setenv get_cmd tftp; " \
  

• "fi; " \
  

• "if mmc dev ${mmcdev}; then "	\
  

• 	"if ${get_cmd} ${update_sd_firmware_filename}; then " \
  

• 		"setexpr fw_sz ${filesize} / 0x200; " \
  

• 		"setexpr fw_sz ${fw_sz} + 1; "	\
  

• 		"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
  

• 	"fi; "	\
  

• "fi\0" \
  

• "update_sf_uboot=" \

• "if tftp $loadaddr $uboot; then " \
  

• 	"sf probe; " \
  

• 	"sf erase 0 0xC0000; " \
  

• 	"sf write $loadaddr 0x400 $filesize; " \
  

• 	"echo 'U-Boot upgraded. Please reset'; " \
  

• "fi\0" \
  

• "setargs=setenv bootargs console=${console},${baudrate} " \

• "root=/dev/${rootdev} rw rootwait cma=128M\0" \
  

• "loadbootscript=" \

• "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
  

• "bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \

• " source\0" \
  

• "loadimage=" \

• "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
  

• "loadfdt=ext2load ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \
• "tryboot=" \

• "if run loadbootscript; then " \
  

• 	"run bootscript; " \
  

• "else " \
  

• 	"if run loadimage; then " \
  

• 		"run doboot; " \
  

• 	"fi; " \
  

• "fi;\0" \
  

• "doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \

• "run setargs; " \
  

• "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  

• 	"if run loadfdt; then " \
  

• 		"bootm ${loadaddr} - ${fdt_addr}; " \
  

• 	"else " \
  

• 		"if test ${boot_fdt} = try; then " \
  

• 			"bootm; " \
  

• 		"else " \
  

• 			"echo WARN: Cannot load the DT; " \
  

• 		"fi; " \
  

• 	"fi; " \
  

• "else " \
  

• 	"bootm; " \
  

• "fi;\0" \
  

• "netargs=setenv bootargs console=${console},${baudrate} " \

• "root=/dev/nfs " \
  

• "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  

• "netboot=echo Booting from net ...; " \

• "run netargs; " \
  

• "if test ${ip_dyn} = yes; then " \
  

• 	"setenv get_cmd dhcp; " \
  

• "else " \
  

• 	"setenv get_cmd tftp; " \
  

• "fi; " \
  

• "${get_cmd} ${image}; " \
  

• "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  

• 	"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  

• 		"bootm ${loadaddr} - ${fdt_addr}; " \
  

• 	"else " \
  

• 		"if test ${boot_fdt} = try; then " \
  

• 			"bootm; " \
  

• 		"else " \
  

• 			"echo WARN: Cannot load the DT; " \
  

• 		"fi; " \
  

• 	"fi; " \
  

• "else " \
  

• 	"bootm; " \
  

• "fi;\0" \
  

+#define CONFIG_BOOTCOMMAND \

• "usb start; " \
• "setenv dev usb; " \
• "setenv devnum 0; " \
• "setenv rootdev sda1; " \
• "run tryboot; " \
• \
• "setenv dev mmc; " \
• "setenv rootdev mmcblk0p1; " \
• \
• "setenv devnum ${sddev}; " \
• "if mmc dev ${devnum}; then " \

• "run tryboot; " \
  

• "setenv rootdev mmcblk1p1; " \
  

• "fi; " \
• \
• "setenv devnum ${emmcdev}; " \
• "if mmc dev ${devnum}; then " \

• "run tryboot; " \
  

• "fi; " \
• \
• "bmode usb; " \

+#define CONFIG_ARP_TIMEOUT 200UL

+/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE

+/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE

+#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000

+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR

+#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE (128 * 1024)

+/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR

+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

+#define CONFIG_SYS_INIT_SP_OFFSET \

• (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

+#define CONFIG_SYS_INIT_SP_ADDR \

• (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

+/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH

+#define CONFIG_ENV_SIZE (8 * 1024)

+#define CONFIG_ENV_IS_IN_SPI_FLASH

+#if defined(CONFIG_ENV_IS_IN_MMC)

You defined CONFIG_ENV_IS_IN_SPI_FLASH. You can drop the CONFIG_ENV_IS_IN_MMC part.

Fixed.

...

+#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 1 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_OFFSET (768 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif

+#define CONFIG_OF_LIBFDT

+#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif

+#define CONFIG_SYS_FSL_USDHC_NUM 3

+/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IPUV3_CLK 260000000 +#define CONFIG_IMX_HDMI +#define CONFIG_IMX_VIDEO_SKIP

+#undef CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) +#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5) +#endif

+/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_MXC_I2C1 +#define CONFIG_SYS_I2C_MXC_I2C2 +#define CONFIG_SYS_I2C_MXC_I2C3

+#ifdef CONFIG_SYS_RECOVERY

I do not find CONFIG_SYS_RECOVERY in uboot upstream code. You may need to drop it.

Regards, Peng.

Removed it since it was only used during development.

Thanks for all the feedback :)

Version 2 of the patch is posted here: http://lists.denx.de/pipermail/u-boot/2016-January/243985.html

Akshay

...

+#undef CONFIG_BOOTCOMMAND

+#undef CONFIG_ENV_IS_IN_SPI_FLASH +#undef CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_IS_NOWHERE

+#define CONFIG_BOOTCOMMAND \

• "setenv dev mmc; " \
• "setenv devnum ${sddev}; " \
• "setenv rootdev mmcblk0p1; " \
• "run tryboot; " \
• \
• "bmode usb; " \

+#endif /* CONFIG_SYS_RECOVERY */

+#endif /* __GE_BX50V3_CONFIG_H */

2.7.0

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