After the commit b9a2a0e2e9c0 ("mmc: Add support for downgrading HS200/HS400 to HS mode"), it add a parameter in mmc_set_card_speed() which indicates that the HS200/HS400 to HS downgrade is happening.
During the HS400 initialization, first select to HS200, and config the related clock rate, then downgrade to HS mode. So here also need to config the downgrade value to be true for two reasons. First, make sure in the function mmc_set_card_speed(), after switch to HS mode, first config the clock rate, then read the EXT_CSD, avoid receiving data of EXT_CSD in HS mode at 200MHz. Second, after issue the MMC_CMD_SWITCH command, it need to wait a bit then switch bus properties.
Test on i.MX8QM MEK board, some Micron eMMC will stuck in transfer mode in this case, and USDHC will never get data transfer complete status, cause the uboot hang.
Signed-off-by: Haibo Chen haibo.chen@nxp.com --- drivers/mmc/mmc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 89b255daf4..456c1b4cc9 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1892,8 +1892,7 @@ static int mmc_select_hs400(struct mmc *mmc) }
/* Set back to HS */ - mmc_set_card_speed(mmc, MMC_HS, false); - mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false); + mmc_set_card_speed(mmc, MMC_HS, true);
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);