Move needed definitions (register descriptions etc.) from include/mpc512x.h into include/asm-ppc/immap_512x.h.
All the rest of include/mpc512x.h are register offset definitions which can be eliminated by proper use of C structures - of course in combination with replacing pointer accesses by I/O accessor calls.
There are only a few register offsets remaining that are needed in cpu/mpc512x/start.S; for these we provide cpu/mpc512x/asm-offsets.h which is intended as a temporary workaround only. In a later patch this file will be removed, too, and then auto-generated from the respective C structs.
Signed-off-by: Wolfgang Denk wd@denx.de Cc: John Rigby jcrigby@gmail.com --- cpu/mpc512x/asm-offsets.h | 15 ++ cpu/mpc512x/start.S | 4 +- include/asm-ppc/immap_512x.h | 324 +++++++++++++++++++++++++++++++++++++++++- include/mpc512x.h | 317 ----------------------------------------- 4 files changed, 341 insertions(+), 319 deletions(-) create mode 100644 cpu/mpc512x/asm-offsets.h
diff --git a/cpu/mpc512x/asm-offsets.h b/cpu/mpc512x/asm-offsets.h new file mode 100644 index 0000000..4b14778 --- /dev/null +++ b/cpu/mpc512x/asm-offsets.h @@ -0,0 +1,15 @@ +/* + * needed for cpu/mpc512x/start.S + * + * These should be auto-generated + */ +#define LPCS0AW 0x0024 +#define SRAMBAR 0x00C4 +#define SWCRR 0x0904 +#define LPC_OFFSET 0x10000 +#define CS0_CONFIG 0x00000 +#define CS_CTRL 0x00020 +#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */ + +#define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 360682d..f7d648d 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -30,12 +30,14 @@ */
#include <config.h> -#include <mpc512x.h> #include <timestamp.h> #include <version.h>
#define CONFIG_521X 1 /* needed for Linux kernel header files*/
+#include <asm/immap_512x.h> +#include "asm-offsets.h" + #include <ppc_asm.tmpl> #include <ppc_defs.h>
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index db6a232..1569b3f 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -25,7 +25,28 @@ #define __IMMAP_512x__
#include <asm/types.h> +#if defined(CONFIG_E300) +#include <asm/e300.h> +#endif
+/* + * System reset offset (PowerPC standard) + */ +#define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET + +#define SPR_5121E 0x80180000 + +/* + * IMMRBAR - Internal Memory Register Base Address + */ +#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ +#define IMMRBAR 0x0000 /* Register offset to immr */ +#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ +#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) + + +#ifndef __ASSEMBLY__ typedef struct law512x { u32 bar; /* Base Addr Register */ u32 ar; /* Attributes Register */ @@ -60,6 +81,8 @@ typedef struct sysconf512x { u8 res5[0xf8]; } sysconf512x_t;
+#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ + /* * Watch Dog Timer (WDT) Registers */ @@ -124,6 +147,34 @@ typedef struct reset512x { u8 res1[0xDC]; } reset512x_t;
+/* RSR - Reset Status Register */ +#define RSR_SWSR 0x00002000 /* software soft reset */ +#define RSR_SWHR 0x00001000 /* software hard reset */ +#define RSR_JHRS 0x00000200 /* jtag hreset */ +#define RSR_JSRS 0x00000100 /* jtag sreset status */ +#define RSR_CSHR 0x00000010 /* checkstop reset status */ +#define RSR_SWRS 0x00000008 /* software watchdog reset status */ +#define RSR_BMRS 0x00000004 /* bus monitop reset status */ +#define RSR_SRS 0x00000002 /* soft reset status */ +#define RSR_HRS 0x00000001 /* hard reset status */ +#define RSR_RES ~(RSR_SWSR | RSR_SWHR |\ + RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ + RSR_BMRS | RSR_SRS | RSR_HRS) + +/* RMR - Reset Mode Register */ +#define RMR_CSRE 0x00000001 /* checkstop reset enable */ +#define RMR_CSRE_SHIFT 0 +#define RMR_RES (~(RMR_CSRE)) + +/* RCR - Reset Control Register */ +#define RCR_SWHR 0x00000002 /* software hard reset */ +#define RCR_SWSR 0x00000001 /* software soft reset */ +#define RCR_RES (~(RCR_SWHR | RCR_SWSR)) + +/* RCER - Reset Control Enable Register */ +#define RCER_CRE 0x00000001 /* software hard reset */ +#define RCER_RES (~(RCER_CRE)) + /* * Clock Module */ @@ -140,6 +191,56 @@ typedef struct clk512x { u8 res1[0xa8]; } clk512x_t;
+/* SPMR - System PLL Mode Register */ +#define SPMR_SPMF 0x0F000000 +#define SPMR_SPMF_SHIFT 24 +#define SPMR_CPMF 0x000F0000 +#define SPMR_CPMF_SHIFT 16 + +/* System Clock Control Register 1 commands */ +#define CLOCK_SCCR1_CFG_EN 0x80000000 +#define CLOCK_SCCR1_LPC_EN 0x40000000 +#define CLOCK_SCCR1_NFC_EN 0x20000000 +#define CLOCK_SCCR1_PATA_EN 0x10000000 +#define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn)) +#define CLOCK_SCCR1_PSCFIFO_EN 0x00008000 +#define CLOCK_SCCR1_SATA_EN 0x00004000 +#define CLOCK_SCCR1_FEC_EN 0x00002000 +#define CLOCK_SCCR1_TPR_EN 0x00001000 +#define CLOCK_SCCR1_PCI_EN 0x00000800 +#define CLOCK_SCCR1_DDR_EN 0x00000400 + +/* System Clock Control Register 2 commands */ +#define CLOCK_SCCR2_DIU_EN 0x80000000 +#define CLOCK_SCCR2_AXE_EN 0x40000000 +#define CLOCK_SCCR2_MEM_EN 0x20000000 +#define CLOCK_SCCR2_USB2_EN 0x10000000 +#define CLOCK_SCCR2_USB1_EN 0x08000000 +#define CLOCK_SCCR2_I2C_EN 0x04000000 +#define CLOCK_SCCR2_BDLC_EN 0x02000000 +#define CLOCK_SCCR2_SDHC_EN 0x01000000 +#define CLOCK_SCCR2_SPDIF_EN 0x00800000 +#define CLOCK_SCCR2_MBX_BUS_EN 0x00400000 +#define CLOCK_SCCR2_MBX_EN 0x00200000 +#define CLOCK_SCCR2_MBX_3D_EN 0x00100000 +#define CLOCK_SCCR2_IIM_EN 0x00080000 + +/* SCFR1 System Clock Frequency Register 1 */ +#define SCFR1_IPS_DIV 0x3 +#define SCFR1_IPS_DIV_MASK 0x03800000 +#define SCFR1_IPS_DIV_SHIFT 23 + +#define SCFR1_PCI_DIV 0x6 +#define SCFR1_PCI_DIV_MASK 0x00700000 +#define SCFR1_PCI_DIV_SHIFT 20 + +/* SCFR2 System Clock Frequency Register 2 */ +#define SCFR2_SYS_DIV 0xFC000000 +#define SCFR2_SYS_DIV_SHIFT 26 + +/* SPCR - System Priority Configuration Register */ +#define SPCR_TBEN 0x00400000 /* E300 core time base unit enable */ + /* * Power Management Control Module */ @@ -266,6 +367,40 @@ typedef struct pci_outbound_window { u8 res2[4]; } pot512x_t;
+/* POTAR - PCI Outbound Translation Address Register */ +#define POTAR_TA_MASK 0x000fffff + +/* POBAR - PCI Outbound Base Address Register */ +#define POBAR_BA_MASK 0x000fffff + +/* POCMR - PCI Outbound Comparision Mask Register */ +#define POCMR_EN 0x80000000 +#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ +#define POCMR_PRE 0x20000000 /* prefetch enable */ +#define POCMR_SBS 0x00100000 /* special byte swap enable */ +#define POCMR_CM_MASK 0x000fffff +#define POCMR_CM_4G 0x00000000 +#define POCMR_CM_2G 0x00080000 +#define POCMR_CM_1G 0x000C0000 +#define POCMR_CM_512M 0x000E0000 +#define POCMR_CM_256M 0x000F0000 +#define POCMR_CM_128M 0x000F8000 +#define POCMR_CM_64M 0x000FC000 +#define POCMR_CM_32M 0x000FE000 +#define POCMR_CM_16M 0x000FF000 +#define POCMR_CM_8M 0x000FF800 +#define POCMR_CM_4M 0x000FFC00 +#define POCMR_CM_2M 0x000FFE00 +#define POCMR_CM_1M 0x000FFF00 +#define POCMR_CM_512K 0x000FFF80 +#define POCMR_CM_256K 0x000FFFC0 +#define POCMR_CM_128K 0x000FFFE0 +#define POCMR_CM_64K 0x000FFFF0 +#define POCMR_CM_32K 0x000FFFF8 +#define POCMR_CM_16K 0x000FFFFC +#define POCMR_CM_8K 0x000FFFFE +#define POCMR_CM_4K 0x000FFFFF + /* * Sequencer */ @@ -315,6 +450,27 @@ typedef struct pcictrl512x { } pcictrl512x_t;
+/* PITAR - PCI Inbound Translation Address Register + */ +#define PITAR_TA_MASK 0x000fffff + +/* PIBAR - PCI Inbound Base/Extended Address Register + */ +#define PIBAR_MASK 0xffffffff +#define PIEBAR_EBA_MASK 0x000fffff + +/* PIWAR - PCI Inbound Windows Attributes Register + */ +#define PIWAR_EN 0x80000000 +#define PIWAR_SBS 0x40000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_RTT_MASK 0x000f0000 +#define PIWAR_RTT_NO_SNOOP 0x00040000 +#define PIWAR_RTT_SNOOP 0x00050000 +#define PIWAR_WTT_MASK 0x0000f000 +#define PIWAR_WTT_NO_SNOOP 0x00004000 +#define PIWAR_WTT_SNOOP 0x00005000 + /* * MSCAN */ @@ -355,13 +511,34 @@ typedef struct i2c512x_dev { u8 res0[0x0C]; } i2c512x_dev_t;
+/* Number of I2C buses */ +#define I2C_BUS_CNT 3 + typedef struct i2c512x { - i2c512x_dev_t dev[3]; + i2c512x_dev_t dev[I2C_BUS_CNT]; volatile u32 icr; volatile u32 mifr; u8 res0[0x98]; } i2c512x_t;
+/* I2Cn control register bits */ +#define I2C_EN 0x80 +#define I2C_IEN 0x40 +#define I2C_STA 0x20 +#define I2C_TX 0x10 +#define I2C_TXAK 0x08 +#define I2C_RSTA 0x04 +#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) + +/* I2Cn status register bits */ +#define I2C_CF 0x80 +#define I2C_AAS 0x40 +#define I2C_BB 0x20 +#define I2C_AL 0x10 +#define I2C_SRW 0x04 +#define I2C_IF 0x02 +#define I2C_RXAK 0x01 + /* * AXE */ @@ -653,6 +830,27 @@ typedef struct ioctrl512x { u8 reserved[0x0cfc]; /* fill to 4096 bytes size */ } ioctrl512x_t;
+/* Indexes in regs array */ +/* Set for DDR */ +#define IOCTRL_MUX_DDR 0x00000036 + +/* IO pin fields */ +#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ +#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ +#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */ +#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */ +#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */ +#define IO_PIN_DS(v) ((v)) /* slew rate */ + +typedef struct iopin_t { + int p_offset; /* offset from IOCTL_MEM_OFFSET */ + int nr_pins; /* number of pins to set this way */ + int bit_or; /* or in the value instead of overwrite */ + u_long val; /* value to write or or */ +}iopin_t; + +void iopin_initialize(iopin_t *,int); + /* * IIM */ @@ -834,6 +1032,51 @@ typedef struct psc512x { #define rfdata_32 rfdata_buffer.buffer_32 } psc512x_t;
+/* PSC FIFO Command values */ +#define PSC_FIFO_RESET_SLICE 0x80 +#define PSC_FIFO_ENABLE_SLICE 0x01 + +/* PSC FIFO Controller Command values */ +#define FIFOC_ENABLE_CLOCK_GATE 0x01 +#define FIFOC_DISABLE_CLOCK_GATE 0x00 + +/* PSC FIFO status */ +#define PSC_FIFO_EMPTY 0x01 + +/* PSC Command values */ +#define PSC_RX_ENABLE 0x01 +#define PSC_RX_DISABLE 0x02 +#define PSC_TX_ENABLE 0x04 +#define PSC_TX_DISABLE 0x08 +#define PSC_SEL_MODE_REG_1 0x10 +#define PSC_RST_RX 0x20 +#define PSC_RST_TX 0x30 +#define PSC_RST_ERR_STAT 0x40 +#define PSC_RST_BRK_CHG_INT 0x50 +#define PSC_START_BRK 0x60 +#define PSC_STOP_BRK 0x70 + +/* PSC status register bits */ +#define PSC_SR_CDE 0x0080 +#define PSC_SR_TXEMP 0x0800 +#define PSC_SR_OE 0x1000 +#define PSC_SR_PE 0x2000 +#define PSC_SR_FE 0x4000 +#define PSC_SR_RB 0x8000 + +/* PSC mode fields */ +#define PSC_MODE_5_BITS 0x00 +#define PSC_MODE_6_BITS 0x01 +#define PSC_MODE_7_BITS 0x02 +#define PSC_MODE_8_BITS 0x03 +#define PSC_MODE_PAREVEN 0x00 +#define PSC_MODE_PARODD 0x04 +#define PSC_MODE_PARFORCE 0x08 +#define PSC_MODE_PARNONE 0x10 +#define PSC_MODE_ENTIMEOUT 0x20 +#define PSC_MODE_RXRTS 0x80 +#define PSC_MODE_1_STOPBIT 0x07 + /* * FIFOC */ @@ -847,6 +1090,76 @@ typedef struct fifoc512x { } fifoc512x_t;
/* + * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs + * + * NOTE: individual PSC units are free to use whatever area (and size) of the + * FIFOC internal memory, so make sure memory areas for FIFO slices used by + * different PSCs do not overlap! + * + * Overall size of FIFOC memory is not documented in the MPC5121e RM, but + * tests indicate that it is 1024 words total. + */ +#define FIFOC_PSC0_TX_SIZE 0x0 /* number of 4-byte words for FIFO slice */ +#define FIFOC_PSC0_TX_ADDR 0x0 +#define FIFOC_PSC0_RX_SIZE 0x0 +#define FIFOC_PSC0_RX_ADDR 0x0 + +#define FIFOC_PSC1_TX_SIZE 0x0 +#define FIFOC_PSC1_TX_ADDR 0x0 +#define FIFOC_PSC1_RX_SIZE 0x0 +#define FIFOC_PSC1_RX_ADDR 0x0 + +#define FIFOC_PSC2_TX_SIZE 0x0 +#define FIFOC_PSC2_TX_ADDR 0x0 +#define FIFOC_PSC2_RX_SIZE 0x0 +#define FIFOC_PSC2_RX_ADDR 0x0 + +#define FIFOC_PSC3_TX_SIZE 0x04 +#define FIFOC_PSC3_TX_ADDR 0x0 +#define FIFOC_PSC3_RX_SIZE 0x04 +#define FIFOC_PSC3_RX_ADDR 0x10 + +#define FIFOC_PSC4_TX_SIZE 0x0 +#define FIFOC_PSC4_TX_ADDR 0x0 +#define FIFOC_PSC4_RX_SIZE 0x0 +#define FIFOC_PSC4_RX_ADDR 0x0 + +#define FIFOC_PSC5_TX_SIZE 0x0 +#define FIFOC_PSC5_TX_ADDR 0x0 +#define FIFOC_PSC5_RX_SIZE 0x0 +#define FIFOC_PSC5_RX_ADDR 0x0 + +#define FIFOC_PSC6_TX_SIZE 0x0 +#define FIFOC_PSC6_TX_ADDR 0x0 +#define FIFOC_PSC6_RX_SIZE 0x0 +#define FIFOC_PSC6_RX_ADDR 0x0 + +#define FIFOC_PSC7_TX_SIZE 0x0 +#define FIFOC_PSC7_TX_ADDR 0x0 +#define FIFOC_PSC7_RX_SIZE 0x0 +#define FIFOC_PSC7_RX_ADDR 0x0 + +#define FIFOC_PSC8_TX_SIZE 0x0 +#define FIFOC_PSC8_TX_ADDR 0x0 +#define FIFOC_PSC8_RX_SIZE 0x0 +#define FIFOC_PSC8_RX_ADDR 0x0 + +#define FIFOC_PSC9_TX_SIZE 0x0 +#define FIFOC_PSC9_TX_ADDR 0x0 +#define FIFOC_PSC9_RX_SIZE 0x0 +#define FIFOC_PSC9_RX_ADDR 0x0 + +#define FIFOC_PSC10_TX_SIZE 0x0 +#define FIFOC_PSC10_TX_ADDR 0x0 +#define FIFOC_PSC10_RX_SIZE 0x0 +#define FIFOC_PSC10_RX_ADDR 0x0 + +#define FIFOC_PSC11_TX_SIZE 0x0 +#define FIFOC_PSC11_TX_ADDR 0x0 +#define FIFOC_PSC11_RX_SIZE 0x0 +#define FIFOC_PSC11_RX_ADDR 0x0 + +/* * SATA */ typedef struct sata512x { @@ -903,4 +1216,13 @@ typedef struct immap { sata512x_t sata; /* Serial ATA */ u8 res13[0xde000]; } immap_t; + +/* provide interface to get PATA base address */ +static inline u32 get_pata_base (void) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + return (u32)(&im->pata); +} +#endif /* __ASSEMBLY__ */ + #endif /* __IMMAP_512x__ */ diff --git a/include/mpc512x.h b/include/mpc512x.h index 0f02293..e4c1d2f 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -21,19 +21,6 @@ #include <asm/e300.h> #endif
-/* System reset offset (PowerPC standard) - */ -#define EXC_OFF_SYS_RESET 0x0100 -#define _START_OFFSET EXC_OFF_SYS_RESET - - -/* IMMRBAR - Internal Memory Register Base Address - */ -#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ -#define IMMRBAR 0x0000 /* Register offset to immr */ -#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ -#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) - /* LAWBAR - Local Access Window Base Address Register */ #define LPBAW 0x0020 /* Register offset to immr */ @@ -46,7 +33,6 @@ #define LPCS6AW 0x003C #define LPCA7AW 0x0040 #define SRAMBAR 0x00C4 -#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */
#define LPC_OFFSET 0x10000
@@ -77,7 +63,6 @@ #define SPCR_PCIHPE_SHIFT (31-3) #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ #define SPCR_PCIPR_SHIFT (31-7) -#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ #define SPCR_TBEN_SHIFT (31-9) #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ #define SPCR_COREPR_SHIFT (31-11) @@ -138,214 +123,9 @@ #define AEATR_TSIZE 0x00000700 /* Transfer Size */ #define AEATR_TTYPE 0x0000001F /* Transfer Type */
-/* RSR - Reset Status Register - */ -#define RSR_SWSR 0x00002000 /* software soft reset */ -#define RSR_SWSR_SHIFT 13 -#define RSR_SWHR 0x00001000 /* software hard reset */ -#define RSR_SWHR_SHIFT 12 -#define RSR_JHRS 0x00000200 /* jtag hreset */ -#define RSR_JHRS_SHIFT 9 -#define RSR_JSRS 0x00000100 /* jtag sreset status */ -#define RSR_JSRS_SHIFT 8 -#define RSR_CSHR 0x00000010 /* checkstop reset status */ -#define RSR_CSHR_SHIFT 4 -#define RSR_SWRS 0x00000008 /* software watchdog reset status */ -#define RSR_SWRS_SHIFT 3 -#define RSR_BMRS 0x00000004 /* bus monitop reset status */ -#define RSR_BMRS_SHIFT 2 -#define RSR_SRS 0x00000002 /* soft reset status */ -#define RSR_SRS_SHIFT 1 -#define RSR_HRS 0x00000001 /* hard reset status */ -#define RSR_HRS_SHIFT 0 -#define RSR_RES ~(RSR_SWSR | RSR_SWHR |\ - RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ - RSR_BMRS | RSR_SRS | RSR_HRS) -/* RMR - Reset Mode Register - */ -#define RMR_CSRE 0x00000001 /* checkstop reset enable */ -#define RMR_CSRE_SHIFT 0 -#define RMR_RES ~(RMR_CSRE) - -/* RCR - Reset Control Register - */ -#define RCR_SWHR 0x00000002 /* software hard reset */ -#define RCR_SWSR 0x00000001 /* software soft reset */ -#define RCR_RES ~(RCR_SWHR | RCR_SWSR) - -/* RCER - Reset Control Enable Register - */ -#define RCER_CRE 0x00000001 /* software hard reset */ -#define RCER_RES ~(RCER_CRE) - -/* SPMR - System PLL Mode Register - */ -#define SPMR_SPMF 0x0F000000 -#define SPMR_SPMF_SHIFT 24 -#define SPMR_CPMF 0x000F0000 -#define SPMR_CPMF_SHIFT 16 - -/* SCFR1 System Clock Frequency Register 1 - */ -#define SCFR1_IPS_DIV 0x3 -#define SCFR1_IPS_DIV_MASK 0x03800000 -#define SCFR1_IPS_DIV_SHIFT 23 - -#define SCFR1_PCI_DIV 0x6 -#define SCFR1_PCI_DIV_MASK 0x00700000 -#define SCFR1_PCI_DIV_SHIFT 20 - -/* SCFR2 System Clock Frequency Register 2 - */ -#define SCFR2_SYS_DIV 0xFC000000 -#define SCFR2_SYS_DIV_SHIFT 26 - /* SCCR - System Clock Control Registers */
-/* System Clock Control Register 1 commands */ -#define CLOCK_SCCR1_CFG_EN 0x80000000 -#define CLOCK_SCCR1_LPC_EN 0x40000000 -#define CLOCK_SCCR1_NFC_EN 0x20000000 -#define CLOCK_SCCR1_PATA_EN 0x10000000 -#define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn)) -#define CLOCK_SCCR1_PSCFIFO_EN 0x00008000 -#define CLOCK_SCCR1_SATA_EN 0x00004000 -#define CLOCK_SCCR1_FEC_EN 0x00002000 -#define CLOCK_SCCR1_TPR_EN 0x00001000 -#define CLOCK_SCCR1_PCI_EN 0x00000800 -#define CLOCK_SCCR1_DDR_EN 0x00000400 - -/* System Clock Control Register 2 commands */ -#define CLOCK_SCCR2_DIU_EN 0x80000000 -#define CLOCK_SCCR2_AXE_EN 0x40000000 -#define CLOCK_SCCR2_MEM_EN 0x20000000 -#define CLOCK_SCCR2_USB2_EN 0x10000000 -#define CLOCK_SCCR2_USB1_EN 0x08000000 -#define CLOCK_SCCR2_I2C_EN 0x04000000 -#define CLOCK_SCCR2_BDLC_EN 0x02000000 -#define CLOCK_SCCR2_SDHC_EN 0x01000000 -#define CLOCK_SCCR2_SPDIF_EN 0x00800000 -#define CLOCK_SCCR2_MBX_BUS_EN 0x00400000 -#define CLOCK_SCCR2_MBX_EN 0x00200000 -#define CLOCK_SCCR2_MBX_3D_EN 0x00100000 -#define CLOCK_SCCR2_IIM_EN 0x00080000 - -/* PSC FIFO Command values */ -#define PSC_FIFO_RESET_SLICE 0x80 -#define PSC_FIFO_ENABLE_SLICE 0x01 - -/* PSC FIFO Controller Command values */ -#define FIFOC_ENABLE_CLOCK_GATE 0x01 -#define FIFOC_DISABLE_CLOCK_GATE 0x00 - -/* PSC FIFO status */ -#define PSC_FIFO_EMPTY 0x01 - -/* PSC Command values */ -#define PSC_RX_ENABLE 0x01 -#define PSC_RX_DISABLE 0x02 -#define PSC_TX_ENABLE 0x04 -#define PSC_TX_DISABLE 0x08 -#define PSC_SEL_MODE_REG_1 0x10 -#define PSC_RST_RX 0x20 -#define PSC_RST_TX 0x30 -#define PSC_RST_ERR_STAT 0x40 -#define PSC_RST_BRK_CHG_INT 0x50 -#define PSC_START_BRK 0x60 -#define PSC_STOP_BRK 0x70 - -/* PSC status register bits */ -#define PSC_SR_CDE 0x0080 -#define PSC_SR_TXEMP 0x0800 -#define PSC_SR_OE 0x1000 -#define PSC_SR_PE 0x2000 -#define PSC_SR_FE 0x4000 -#define PSC_SR_RB 0x8000 - -/* PSC mode fields */ -#define PSC_MODE_5_BITS 0x00 -#define PSC_MODE_6_BITS 0x01 -#define PSC_MODE_7_BITS 0x02 -#define PSC_MODE_8_BITS 0x03 -#define PSC_MODE_PAREVEN 0x00 -#define PSC_MODE_PARODD 0x04 -#define PSC_MODE_PARFORCE 0x08 -#define PSC_MODE_PARNONE 0x10 -#define PSC_MODE_ENTIMEOUT 0x20 -#define PSC_MODE_RXRTS 0x80 -#define PSC_MODE_1_STOPBIT 0x07 - -/* - * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs - * - * NOTE: individual PSC units are free to use whatever area (and size) of the - * FIFOC internal memory, so make sure memory areas for FIFO slices used by - * different PSCs do not overlap! - * - * Overall size of FIFOC memory is not documented in the MPC5121e RM, but - * tests indicate that it is 1024 words total. - */ -#define FIFOC_PSC0_TX_SIZE 0x0 /* number of 4-byte words for FIFO slice */ -#define FIFOC_PSC0_TX_ADDR 0x0 -#define FIFOC_PSC0_RX_SIZE 0x0 -#define FIFOC_PSC0_RX_ADDR 0x0 - -#define FIFOC_PSC1_TX_SIZE 0x0 -#define FIFOC_PSC1_TX_ADDR 0x0 -#define FIFOC_PSC1_RX_SIZE 0x0 -#define FIFOC_PSC1_RX_ADDR 0x0 - -#define FIFOC_PSC2_TX_SIZE 0x0 -#define FIFOC_PSC2_TX_ADDR 0x0 -#define FIFOC_PSC2_RX_SIZE 0x0 -#define FIFOC_PSC2_RX_ADDR 0x0 - -#define FIFOC_PSC3_TX_SIZE 0x04 -#define FIFOC_PSC3_TX_ADDR 0x0 -#define FIFOC_PSC3_RX_SIZE 0x04 -#define FIFOC_PSC3_RX_ADDR 0x10 - -#define FIFOC_PSC4_TX_SIZE 0x0 -#define FIFOC_PSC4_TX_ADDR 0x0 -#define FIFOC_PSC4_RX_SIZE 0x0 -#define FIFOC_PSC4_RX_ADDR 0x0 - -#define FIFOC_PSC5_TX_SIZE 0x0 -#define FIFOC_PSC5_TX_ADDR 0x0 -#define FIFOC_PSC5_RX_SIZE 0x0 -#define FIFOC_PSC5_RX_ADDR 0x0 - -#define FIFOC_PSC6_TX_SIZE 0x0 -#define FIFOC_PSC6_TX_ADDR 0x0 -#define FIFOC_PSC6_RX_SIZE 0x0 -#define FIFOC_PSC6_RX_ADDR 0x0 - -#define FIFOC_PSC7_TX_SIZE 0x0 -#define FIFOC_PSC7_TX_ADDR 0x0 -#define FIFOC_PSC7_RX_SIZE 0x0 -#define FIFOC_PSC7_RX_ADDR 0x0 - -#define FIFOC_PSC8_TX_SIZE 0x0 -#define FIFOC_PSC8_TX_ADDR 0x0 -#define FIFOC_PSC8_RX_SIZE 0x0 -#define FIFOC_PSC8_RX_ADDR 0x0 - -#define FIFOC_PSC9_TX_SIZE 0x0 -#define FIFOC_PSC9_TX_ADDR 0x0 -#define FIFOC_PSC9_RX_SIZE 0x0 -#define FIFOC_PSC9_RX_ADDR 0x0 - -#define FIFOC_PSC10_TX_SIZE 0x0 -#define FIFOC_PSC10_TX_ADDR 0x0 -#define FIFOC_PSC10_RX_SIZE 0x0 -#define FIFOC_PSC10_RX_ADDR 0x0 - -#define FIFOC_PSC11_TX_SIZE 0x0 -#define FIFOC_PSC11_TX_ADDR 0x0 -#define FIFOC_PSC11_RX_SIZE 0x0 -#define FIFOC_PSC11_RX_ADDR 0x0 - /* IO Control Register */ #define IOCTL_MEM 0x000 @@ -546,27 +326,6 @@ #define IOCTL_USB2_VBUS_PWR_SELECT 0x30C #define IOCTL_USB2_PHY_DRVV_BUS 0x310
-#ifndef __ASSEMBLY__ - - -/* IO pin fields */ -#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ -#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ -#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */ -#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */ -#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */ -#define IO_PIN_DS(v) ((v)) /* slew rate */ - -typedef struct iopin_t { - int p_offset; /* offset from IOCTL_MEM_OFFSET */ - int nr_pins; /* number of pins to set this way */ - int bit_or; /* or in the value instead of overwrite */ - u_long val; /* value to write or or */ -}iopin_t; - -void iopin_initialize(iopin_t *,int); -#endif - /* Indexes in regs array */ /* Set for DDR */ #define IOCTRL_MUX_DDR 0x00000036 @@ -599,84 +358,8 @@ void iopin_initialize(iopin_t *,int); #define IIM_PROTECTION 0x000000e8 #define IIM_FMAX 31
-/* Number of I2C buses */ -#define I2C_BUS_CNT 3 - -/* I2Cn control register bits */ -#define I2C_EN 0x80 -#define I2C_IEN 0x40 -#define I2C_STA 0x20 -#define I2C_TX 0x10 -#define I2C_TXAK 0x08 -#define I2C_RSTA 0x04 -#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) - -/* I2Cn status register bits */ -#define I2C_CF 0x80 -#define I2C_AAS 0x40 -#define I2C_BB 0x20 -#define I2C_AL 0x10 -#define I2C_SRW 0x04 -#define I2C_IF 0x02 -#define I2C_RXAK 0x01 - -/* POTAR - PCI Outbound Translation Address Register - */ -#define POTAR_TA_MASK 0x000fffff - -/* POBAR - PCI Outbound Base Address Register - */ -#define POBAR_BA_MASK 0x000fffff - -/* POCMR - PCI Outbound Comparision Mask Register - */ -#define POCMR_EN 0x80000000 -#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ -#define POCMR_PRE 0x20000000 /* prefetch enable */ -#define POCMR_SBS 0x00100000 /* special byte swap enable */ -#define POCMR_CM_MASK 0x000fffff -#define POCMR_CM_4G 0x00000000 -#define POCMR_CM_2G 0x00080000 -#define POCMR_CM_1G 0x000C0000 -#define POCMR_CM_512M 0x000E0000 -#define POCMR_CM_256M 0x000F0000 -#define POCMR_CM_128M 0x000F8000 -#define POCMR_CM_64M 0x000FC000 -#define POCMR_CM_32M 0x000FE000 -#define POCMR_CM_16M 0x000FF000 -#define POCMR_CM_8M 0x000FF800 -#define POCMR_CM_4M 0x000FFC00 -#define POCMR_CM_2M 0x000FFE00 -#define POCMR_CM_1M 0x000FFF00 -#define POCMR_CM_512K 0x000FFF80 -#define POCMR_CM_256K 0x000FFFC0 -#define POCMR_CM_128K 0x000FFFE0 -#define POCMR_CM_64K 0x000FFFF0 -#define POCMR_CM_32K 0x000FFFF8 -#define POCMR_CM_16K 0x000FFFFC -#define POCMR_CM_8K 0x000FFFFE -#define POCMR_CM_4K 0x000FFFFF - -/* PITAR - PCI Inbound Translation Address Register - */ -#define PITAR_TA_MASK 0x000fffff - -/* PIBAR - PCI Inbound Base/Extended Address Register - */ -#define PIBAR_MASK 0xffffffff -#define PIEBAR_EBA_MASK 0x000fffff - /* PIWAR - PCI Inbound Windows Attributes Register */ -#define PIWAR_EN 0x80000000 -#define PIWAR_SBS 0x40000000 -#define PIWAR_PF 0x20000000 -#define PIWAR_RTT_MASK 0x000f0000 -#define PIWAR_RTT_NO_SNOOP 0x00040000 -#define PIWAR_RTT_SNOOP 0x00050000 -#define PIWAR_WTT_MASK 0x0000f000 -#define PIWAR_WTT_NO_SNOOP 0x00004000 -#define PIWAR_WTT_SNOOP 0x00005000 #define PIWAR_IWS_MASK 0x0000003F #define PIWAR_IWS_4K 0x0000000B #define PIWAR_IWS_8K 0x0000000C