The omap2420-h4 board is using a RAM based address as the linker location for code. This is causing several problems when attempting to run the latest u-boot code base on this board from flash. Update the default linker location for code to be in NOR flash. Please note that OMAP maps the NOR flash to address 0x08000000 by default and so use this as the default address for the NOR flash.
Also remove legacy code that attempts to calculate where in flash the sdata structure, that holds the memory interface configuration data, is located. By changing the default linker location for code to flash this is no longer necessary.
Signed-off-by: Jon Hunter jon-hunter@ti.com --- arch/arm/include/asm/arch-omap24xx/omap2420.h | 6 +++--- board/ti/omap2420h4/config.mk | 4 ++-- board/ti/omap2420h4/mem.c | 13 ------------- include/configs/omap2420h4.h | 2 +- 4 files changed, 6 insertions(+), 19 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap24xx/omap2420.h b/arch/arm/include/asm/arch-omap24xx/omap2420.h index d8d5647..5724f5d 100644 --- a/arch/arm/include/asm/arch-omap24xx/omap2420.h +++ b/arch/arm/include/asm/arch-omap24xx/omap2420.h @@ -212,9 +212,9 @@ # define H4_CS1_BASE 0x04000000 /* debug board */ # define H4_CS2_BASE 0x0A000000 /* wifi board */ #else -# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x08000000 /* debug board */ -# define H4_CS2_BASE 0x0A000000 /* wifi board */ +# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ +# define H4_CS1_BASE 0x04000000 /* debug board */ +# define H4_CS2_BASE 0x0C000000 /* wifi board */ #endif
/* base address for indirect vectors (internal boot mode) */ diff --git a/board/ti/omap2420h4/config.mk b/board/ti/omap2420h4/config.mk index ca5ebdf..e5dff69 100644 --- a/board/ti/omap2420h4/config.mk +++ b/board/ti/omap2420h4/config.mk @@ -14,7 +14,7 @@ # (mem base + reserved)
# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80e80000 +#CONFIG_SYS_TEXT_BASE = 0x80e80000
# Used with full SRAM boot. # This is either with a GP system or a signed boot image. @@ -24,5 +24,5 @@ CONFIG_SYS_TEXT_BASE = 0x80e80000
# Handy to get symbols to debug ROM version. #CONFIG_SYS_TEXT_BASE = 0x0 -#CONFIG_SYS_TEXT_BASE = 0x08000000 +CONFIG_SYS_TEXT_BASE = 0x08000000 #CONFIG_SYS_TEXT_BASE = 0x04000000 diff --git a/board/ti/omap2420h4/mem.c b/board/ti/omap2420h4/mem.c index c8b4186..ba3f12a 100644 --- a/board/ti/omap2420h4/mem.c +++ b/board/ti/omap2420h4/mem.c @@ -200,19 +200,6 @@ void do_sdrc_init(u32 offset, u32 early)
__asm__ __volatile__("": : :"memory"); /* limit compiler scope */
- /* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx. - * If we are running in flash prior to relocation and we use data - * here which is not pc relative we need to get the address correct. - * We need to find the current flash mapping to dress up the initial - * pointer load. As long as this is const data we should be ok. - */ - if((early) && running_in_flash()){ - sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base()); - /* NOR internal boot offset is 0x4000 from xloader signature */ - if(running_from_internal_boot()) - sdata = (sdrc_data_t *)((u32)sdata + 0x4000); - } - if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) { if(mtype == DDR_COMBO){ pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */ diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 1abf259..cb050ab 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -220,7 +220,7 @@ #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */ #else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_128K) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_256K) #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE #define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */