Hi all,
I was about to submit a patch to add support for an MPC8641D based board, but I ran into a problem in tsec.c when I set optimization back to -Os. (With optimization set to -O1 or -O2, the problem does not appear.)
If I let the code run from reset, it halts at address 0ffe18bc (tsec.c line 309) and all the GPRs appear to be 0xffffffff. If I place an internal hardware breakpoint at 0ffe18bc, and run from reset, it hits the breakpoint 4 times (there is a quad phy on the board). If I resume after the 4th break, the code runs to the u-boot prompt, counts down and loads linux/ramdisk/dtb from flash and boots into linux correctly.
At first I thought it might be a DRAM problem, possibly not letting it "settle" long enough after initialization, so I let it hit the breakpoint (everything looked good), removed the breakpoint and let it resume and I see the same problem.
Here's the snippet of code that's giving me the trouble:
302 /* Reset MII (due to new addresses) */ 303 priv->phyregs->miimcfg = MIIMCFG_RESET; 0ffe1890: lwz r9,4(r31) 0ffe1894: lis r0,-0x8000 0ffe1898: stw r0,0x520(r9) 304 asm("sync"); 0ffe189c: sync 305 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; 0ffe18a0: li r0,3 0ffe18a4: stw r0,0x520(r9) 306 asm("sync"); 0ffe18a8: sync 307 while (priv->phyregs->miimind & MIIMIND_BUSY) ; 0ffe18ac: lwz r0,0x534(r9) 0ffe18b0: andi. r11,r0,1 0ffe18b4: bne 0xFFE18AC 308 309 if (0 == relocated) 0ffe18b8: lwz r9,-0x7FDC(r30) 0ffe18bc: lwz r0,0(r9) 0ffe18c0: cmpi 7,r0,0 0ffe18c4: bne cr7,0xFFE1984 1316 /* First thing's first: relocate the pointers to the 1317 * PHY command structures (the structs were done) */ 1318 phy_info[i] = (struct phy_info *)((uint) phy_info[i] 0ffe18c8: lwz r27,-0x8000(r30) 0ffe18cc: mr r3,r29 0ffe18d0: b 0xFFE196C 0ffe18d4: lwz r9,0x18(r3) 1319 + gd->reloc_off); 1320 phy_info[i]->name += gd->reloc_off; 0ffe18d8: lwz r4,0x18(r3) 0ffe18dc: add r9,r0,r9
Thanks in advance, Joe