On 23. 05. 19 15:54, Luca Ceresoli wrote:
Hi,
On 22/05/19 12:24, Michal Simek wrote:
On 10. 05. 19 10:15, Luca Ceresoli wrote:
Avnet UltraZed-EV Starter Kit is composed by the UltraZed-EV SoM and the only publicly-available compatible carrier card. The SoM is based on the EV version of the Xilinx ZynqMP SoC+FPGA.
The psu_init_gpl.c file has been generated from the board definition files at [0] using Vivado 2018.3. It has then minimized by tools/zynqmp_psu_init_minimize.sh and slightly fixed manually.
[0] https://github.com/Avnet/bdf/tree/3686c9ff7d2f0467fb4fcf39f861b8d6ff183b12/u...
Signed-off-by: Luca Ceresoli luca@lucaceresoli.net
Whole patchset tested on:
- current u-boot/master, as is
- current u-boot-microblaze/master
- current u-boot-microblaze/master with the addtion of commit f89d6133eef2 ("configs: move CONFIG_SPL_TEXT_BASE to Kconfig")
[...]
diff --git a/arch/arm/dts/avnet-ultrazedev.dts b/arch/arm/dts/avnet-ultrazedev.dts new file mode 100644 index 000000000000..34d506a28e88 --- /dev/null +++ b/arch/arm/dts/avnet-ultrazedev.dts
[...]
+/* I2C peripherals on carrier card */
This is the biggest issue I have with this patch. It is SOM which should be described in separate file and then we have carried board. That's why please separate DTS file.
Absolutely! Will do.
+&i2c_cc {
- /* Microchip 24AA025E48T-I/OT: 2K I2C Serial EEPROMs with EUI-48 */
- eeprom: eeprom@51 {
compatible = "at,24c02", "i2c-eeprom";reg = <0x51>;- };
- /* Versa Clock 5P49V5935B */
- vc5: clock-generator@6a {
compatible = "idt,5p49v5935";reg = <0x6a>;#clock-cells = <1>;- };
+};
+/* Ethernet:
- Marvell 88E1512-A0-NNP2I000 PHY on SOM
- RJ-45 on Carrier Card
- */
This is interesting.
+&gem3 {
- status = "okay";
- phy-mode = "rgmii-id";
+};
Well, the phy-mode is related to the MAC-PHY link, while the existence of a connector is carrier-dependent. So I think the right thing to do here is:
In the SOM dtsi:
&gem3 { phy-mode = "rgmii-id"; };
and in the carrier dts:
&gem3 { status = "okay"; };
Does it look OK?
I have looked at schematics and SOM dt should have phy-mode , phy address + phy flags if any. And yes - you can enable status if there is connector on carrier board.
diff --git a/board/xilinx/zynqmp/avnet-ultrazedev/psu_init_gpl.c b/board/xilinx/zynqmp/avnet-ultrazedev/psu_init_gpl.c new file mode 100644 index 000000000000..44e683dcee3f --- /dev/null +++ b/board/xilinx/zynqmp/avnet-ultrazedev/psu_init_gpl.c
[...]
+static int init_serdes(void) +{
I can't see any description for serdes in DT. That's why you can likely remove the whole this function if you are not using GTs.
I see. Actually the board has USB, but I didn't use it, so it's not in DT. I'll remove all the serdes code in v2.
diff --git a/configs/avnet_ultrazedev_defconfig b/configs/avnet_ultrazedev_defconfig new file mode 100644 index 000000000000..932be1cfb07a --- /dev/null +++ b/configs/avnet_ultrazedev_defconfig @@ -0,0 +1,64 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_ZYNQMP_TWO_SDHCI=y +CONFIG_DEBUG_UART=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTDELAY=0 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_TEXT_BASE=0xfffc0000 +CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_PROMPT="ZynqMP> " +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="avnet-ultrazedev" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK_ZYNQMP=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xfa +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SF_DUAL_FLASH=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_SPI=y +CONFIG_ZYNQMP_GQSPI=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
FYI: I need to take a look how to remove these board stuff and have only one generic defconfig for all these boards.
Good idea!
Anyway I forget to mentioned one thing. Are you willing to test this board and keep it updated? I don't want to end up in situation where I am with microzed and picozed which I am not able to test myself.
Thanks, Michal