Hi Stefan,
On 16/04/2014 15:36, Stefan Agner wrote:
Can you better explain this ? There is only one board in mainline with vf610. CONFIG_SYS_TEXT_BASE is set to 0x3f008000. I cannot get the offset in your example. Are you referring to NAND page ? But if the header must be aligned with the NAND page, this is pretty bad because we have to adjust the header depending on the selected NAND chip. I do not see this limitation in the manual.
I've not submitted my board yet, I altered it to use 0x3f400800 as CONFIG_SYS_TEXT_BASE. I just realize that a header length of 0x7fc doesn't fit with 0x3f400404 even though (that would be 0x3f400004 if anything). But the mkimage utility reports Load Address: 3f400420 Entry Point: 3f400800 I'm a bit confused now, why is the header only 0x400 now?
Ok I checked this again, the header total size is _not_ 0x7fc, thats imximage_init_loadsize, which is the header size + flash load size (0x400 for NAND).
The header total size is 0x3fc (sizeof(imx_header_v2_t)) right now. This patch would make alter it to be exactly 0x400.
This renforces my suspect. Making the image bigger, it seems that the SOC loads more data as before.
However, reading in the manual, the initial load image (what the SOC should load initially) is 4K (Table 19.37), and adding 4 bytes should have no influence.
In case this discussion ends up adding this padding word, I will send a new patch with correct numbers and better description.
It is not clear what is the cause of the issue and then which is the solution. Adding the pad at the moment seems only a work-around for you.
Best regards, Stefano Babic