On Thu, Aug 26, 2004 at 01:30:19AM -0700, Getz, Robin wrote:
What I was thinking of doing was defining some reserved memory locations of the processor as FLASH, and handle this in /board/specific/flash.c - a flash write to 6 memory locations will actually set the MAC address in the EEPROM attached to the LAN91111.
Patche bellow adds new command - sea - Store Ethernet Address :-) sea 11:22:33:44:55:66 Address is writen into EEPROM connected to LAN91C111 chip (there are some not necessary changes - result of some testing)
Best regards, ladis
Index: common/cmd_net.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/common/cmd_net.c,v retrieving revision 1.13 diff -u -r1.13 cmd_net.c --- common/cmd_net.c 9 Jun 2004 12:42:26 -0000 1.13 +++ common/cmd_net.c 26 Aug 2004 09:11:20 -0000 @@ -279,4 +279,30 @@ ); #endif /* CFG_CMD_CDP */
+extern int set_rom_mac (char *v_rom_mac); + +int do_sea (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i; + char *s, *e, eaddr[6]; + + if (argc != 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + s = argv[1]; + /* turn string into mac value */ + for (i = 0; i < 6; ++i) { + eaddr[i] = simple_strtoul(s, &e, 16); + s = (*e) ? e+1 : e; + } + + return set_rom_mac(eaddr); +} + +U_BOOT_CMD( + sea, 2, 1, do_sea, + "sea\t- Store Ethernet Address\n", +); + #endif /* CFG_CMD_NET */ Index: drivers/smc91111.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/drivers/smc91111.c,v retrieving revision 1.17 diff -u -r1.17 smc91111.c --- drivers/smc91111.c 9 Jul 2004 22:51:02 -0000 1.17 +++ drivers/smc91111.c 26 Aug 2004 09:11:26 -0000 @@ -432,15 +432,9 @@ { PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
- /* This resets the registers mostly to defaults, but doesn't - affect EEPROM. That seems unnecessary */ - SMC_SELECT_BANK (0); - SMC_outw (RCR_SOFTRST, RCR_REG); - /* Setup the Configuration Register */ /* This is necessary because the CONFIG_REG is not affected */ /* by a soft reset */ - SMC_SELECT_BANK (1); #if defined(CONFIG_SMC91111_EXT_PHY) SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); @@ -448,6 +442,10 @@ SMC_outw (CONFIG_DEFAULT, CONFIG_REG); #endif
+ /* This resets the registers mostly to defaults, but doesn't + affect EEPROM. That seems unnecessary */ + SMC_SELECT_BANK (0); + SMC_outw (RCR_SOFTRST, RCR_REG);
/* Release from possible power-down state */ /* Configuration register is not affected by Soft Reset */ @@ -1548,13 +1546,55 @@ int valid_mac = 0;
SMC_SELECT_BANK (1); + SMC_outw ((SMC_inw (CTL_REG) | CTL_RELOAD) & (~CTL_EEPROM_SELECT), CTL_REG); + i = 10; + while (SMC_inw (CTL_REG) & CTL_RELOAD) { + if (!--i) { + printf ("Failed reload MAC addr\n"); + return 0; + } + udelay(100); + } + for (i=0; i<6; i++) { v_rom_mac[i] = SMC_inb ((ADDR0_REG + i)); valid_mac |= v_rom_mac[i]; }
+ PRINTK2("SMC eeprom read::\n" ); + PRINTK2(" MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", + v_rom_mac[0], v_rom_mac[1], + v_rom_mac[2], v_rom_mac[3], + v_rom_mac[4], v_rom_mac[5]) ; + + PRINTK2(" Base: %04x\n", SMC_inw (BASE_REG) ); + PRINTK2(" Gp: %04x\n", SMC_inw (GP_REG) ); + return (valid_mac ? 1 : 0); #endif } + +int set_rom_mac (char *v_rom_mac) +{ + int i, timeout; + + printf ("\nStoring MAC address.\n"); + + for (i = 0; i < 3; i++) { + SMC_SELECT_BANK (2); + SMC_outw ( 0x20 + i, PTR_REG ); + SMC_SELECT_BANK (1); + SMC_outw ( *(((u16 *)v_rom_mac)+i), GP_REG ); + SMC_outw (SMC_inw (CTL_REG) | CTL_STORE | CTL_EEPROM_SELECT, CTL_REG); + timeout = 100; + while (SMC_inw (CTL_REG) & CTL_STORE && --timeout) + udelay(100); + if (timeout == 0) { + printf ("Failed to store MAC address\n"); + break; + } + } +} + #endif /* CONFIG_DRIVER_SMC91111 */ Index: drivers/smc91111.h =================================================================== RCS file: /cvsroot/u-boot/u-boot/drivers/smc91111.h,v retrieving revision 1.10 diff -u -r1.10 smc91111.h --- drivers/smc91111.h 9 Jun 2004 15:37:24 -0000 1.10 +++ drivers/smc91111.h 26 Aug 2004 09:11:28 -0000 @@ -374,7 +374,7 @@ #define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */
/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */ -#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) +#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN | CONFIG_NO_WAIT)
/* Base Address Register */