Hi Raymond,
On Wed, Dec 27, 2023 at 4:06 PM Raymond Mao raymond.mao@linaro.org wrote:
Hi Simon,
On Tue, 26 Dec 2023 at 04:48, Simon Glass sjg@chromium.org wrote:
Hi Raymond,
On Fri, Dec 22, 2023 at 9:31 PM Raymond Mao raymond.mao@linaro.org wrote:
Add bloblist_check_reg_conv() to check whether the bloblist is compliant to the register conventions defined in Firmware Handoff specification. This API can be used for all Arm platforms.
Signed-off-by: Raymond Mao raymond.mao@linaro.org
Changes in v2
- Refactor of bloblist_check_reg_conv().
Changes in v3
- bloblist_check_reg_conv() returns -ENOENT if OF_BOARD is disabled.
common/bloblist.c | 13 +++++++++++++ include/bloblist.h | 12 ++++++++++++ 2 files changed, 25 insertions(+)
diff --git a/common/bloblist.c b/common/bloblist.c index 625e480f6b..ba17dd851a 100644 --- a/common/bloblist.c +++ b/common/bloblist.c @@ -542,3 +542,16 @@ int bloblist_maybe_init(void)
return 0;}
+int bloblist_check_reg_conv(ulong rfdt, ulong rzero) +{
if (!IS_ENABLED(CONFIG_OF_BOARD))return -ENOENT;if (rzero || rfdt != (ulong)bloblist_find(BLOBLISTT_CONTROL_FDT, 0)) {gd->bloblist = NULL; /* Reset the gd bloblist pointer */return -EIO;}Where does the magic 4a0fb10b value get checked?
The magic and version of register conventions cannot be checked now since there is a bug in the spec. PSB:
X1[23:0]: set to the TL signature (4a0f_b10b)
That should say 0f_b10b
X1[31:24]: version of the register convention used. Set to 1 for the AArch64 convention specified in this document.
Signature (4a0f_b10b) takes all [31:0] and no space for version of the register convention. This needs to be updated on TF-A and OP-TEE as well after the spec is updated. For now I will just skip the checking.
We should fix the spec instead.
Regards, Simon