Thanks for any pointers.
So here is my current setup, 2 460ex parts bussed together via the PCI bus. The master boots u-boot via flash, reserves some memory, and boots linux. A user process then maps that memory and loads a "flash image" into it. The PIM and POM registers on the master and slave processor are then configured. The slave is setup to enable bus mastering and then its boot is started. I see all the instructions being fetched across the PCI bus correctly (I've made loops and things to confirm that everything is executed on the slave properly). As I follow the instructions across the PCI bus I see it start at the usual location, then jump to FFFFF000 and start going. It makes it all the way to FFFFF29C and then nothing comes across the PCI bus. When I check the code to see where that is, it is the configuration of the TLB entries in init.S (which is almost exactly the same as the init.S for canyonlands). It seems that I've got something setup wrong and that is inhibiting the CPU from any more fetches on the PCI bus. The only TLB entry that I've changed from the canyonlands is the very first one to the following:
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, \ CONFIG_SYS_BOOT_BASE_ADDR, 0xC, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
CONFIG_SYS_BOOT_BASE_ADDR is 0xFF000000 0xC is the space that according to the datasheet is the location of the PCI space. It is the same address that I am using for the POMs so it at least behaves as expected for the initial part of the boot.
I did not see anything else that I *knew* required modification but I was a little unsure about the PCI space TLB entry. Is there another place in the code I need to be modifying things? This happens early so the choices look to be a limited as to what could be wrong. I've also tried the abatron, but it seems to misbehave when using this boot mode.
Thanks,