On Tue, Mar 31, 2009 at 2:21 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
U-Boot 1.1.6 is quite old (more than 2 years old) please try to the current
version I know, but that's the one we use... For now, everything works fine.
is your SOC in the Mainline? if you can tell us which one it's and if it is mainline in U-Boot or Linux? we could take a look on the code
Nope, actually it is a custom chip based on ARM9. Most of other things are proprietery.
in linux yes in u-boot some arch do it but not the arm9
In Linux for sure, but we have MMU setup in Linux, and it is beyond my knowledge. I am concentrated on as-simple-as-can-be DCache switch on, to speed up operations of copying Linux image PRIOR to kernel boot.
IMHO your boot problem is more in linux than in U-Boot
To be clear - I am experiencing long delay in reading peripheral regs. I am reading some registers in a loop, so it takes long time for each access. After that I also noticed that giving a value to any variable takes long time, so it makes me suspect that SDRAM access is very slow. For example, calling get_timer(0) takes the time of over 1000 cycles!
So, quite independantly of Linux, I want to speed up Flash and SDRAM R/W, as well as R/W of peripherals regs in the loop by introducing DCache. Then I saw that for ARM9 to enable DCache one must setup and enable MMU also, and it becomes mess, because I can find any examples in U-Boot and it seem pretty complex to me.
To underline, my intention of enabling DCache in U-Boot has nothing to do with Linux, because I will switch off caches anyway before boot. I just want to use DCache while read and write operations prior to calling kernel boot.
but until we can take a look on the code it will be hard to known
Which code would help? I do not have anything yet regarding the setup. I do not know where to start. For the time, I am examining CP15 coprocessor manipulations in cpu/arm926, which enables/disables cache (even function that you mentioned, cleanup_before_linux() is defined here). In cpu/arm920t/cpu.c i found these lines, for example :
#ifdef USE_920T_MMU /* It makes no sense to use the dcache if the MMU is not enabled */ void dcache_enable (void) { ulong reg;
reg = read_p15_c1 (); cp_delay (); write_p15_c1 (reg | C1_DC); }
I tried calling function dcache_enable () when I enter my driver which does extensive R/W on peripheral regs (and on SDRAM), but off course - it does not work. Even comment says so :). In ARM manual I found:
CP15 C bit M bit 0 0 DCache disabled. All data accesses are to the external memory.
1 0 DCache enabled, MMU disabled. The C bit is overriden by the M bit setting, which means that the DCache is effectively disabled. All data accesses are noncachable, nonbufferable, with no protection checks. All addresses are flat mapped, that is VA = MVA = PA.
1 1 DCache enabled, MMU enabled. All data accesses are cachable or noncachable depending on the page descriptor C bit and B bit (see Table 4-4), and protection checks are performed. All addresses are remapped from VA to PA, depending on the MMU page table entry, that is the VA is translated to an MVA, and the MVA is remapped to a PA.
So, started digging with a hope that somebody alredy implemented this in U-Boot, so I can copy/paste code in my cpu set-up, or, better yet, call a set of C functions (similar to dcache_enable), to set-up MMU, and in the end just call dcache_enable() to do the magic of enabling DCache.
Best regards, Drasko