On Fri, Oct 2, 2015 at 8:10 AM, Fabio Estevam festevam@gmail.com wrote:
On Fri, Oct 2, 2015 at 1:30 AM, Wolfgang Denk wd@denx.de wrote:
In message CAOMZO5CAQXVzpX9mW7uHKB98JnMBeuT3ZjiUe4-V4=adjRk0zg@mail.gmail.com you But if we agree that both are LE accessors, and that the register is BE, then how does it work at all - we would be writing the wrong bit?
Watchdog on LS1021 works by accident rather than by design.
What we are trying to do is to avoid the regression on LS1021 for the 2015.10 release.
Then a proper watchdog driver implementation is needed for 2016.01 so that it takes care of the endianness.
Is this approach acceptable?
Or what about providing a reset_cpu() for LS102x that uses the proper endianness? Would this be a better approach?
Sinan, does it work?
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -13,6 +13,7 @@ #include <tsec.h> #include <netdev.h> #include <fsl_esdhc.h> +#include <config.h>
#include "fsl_epu.h"
@@ -354,3 +355,25 @@ void smp_kick_all_cpus(void) asm volatile("sev"); } #endif + +struct watchdog_regs { + u16 wcr; /* Control */ + u16 wsr; /* Service */ + u16 wrsr; /* Reset Status */ +}; + +#define WCR_WDE 0x04 /* WDOG enable */ +void reset_cpu(ulong addr) +{ + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + + out_be16(&wdog->wcr, WCR_WDE); + + out_be16(&wdog->wsr, 0x5555); + out_be16(&wdog->wsr, 0xaaaa); /* load minimum 1/2 second timeout */ + while (1) { + /* + * spin for .5 seconds before reset + */ + } +} diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 9e9cb55..a007ae8 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -7,7 +7,7 @@
obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o -ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610 ls102xa)) +ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610)) obj-y += imx_watchdog.o endif obj-$(CONFIG_S5P) += s5p_wdt.o