OPOS6UL is an i.MX6UL based SoM with 256MB RAM, 4GB eMMC and an ethernet phy. OPOS6ULDev is carrier board for the OPOS6UL.
U-Boot SPL 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09) Trying to boot from MMC1
U-Boot 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09 +0100)
CPU: Freescale i.MX6UL rev1.0 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 40C Reset cause: POR Model: Armadeus Systems OPOS6UL SoM on OPOS6ULDev board DRAM: 256 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Video: 800x480x18 In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0
Signed-off-by: Sébastien Szymanski sebastien.szymanski@armadeus.com --- arch/arm/cpu/armv7/mx6/Kconfig | 15 ++ arch/arm/cpu/armv7/mx6/Makefile | 1 + arch/arm/cpu/armv7/mx6/opos6ul.c | 302 +++++++++++++++++++++++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx6ul-opos6ul.dtsi | 192 +++++++++++++++ arch/arm/dts/imx6ul-opos6uldev.dts | 412 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/opos6ul.h | 16 ++ board/armadeus/opos6uldev/Kconfig | 15 ++ board/armadeus/opos6uldev/MAINTAINERS | 6 + board/armadeus/opos6uldev/Makefile | 6 + board/armadeus/opos6uldev/board.c | 125 ++++++++++ configs/opos6uldev_defconfig | 85 +++++++ include/configs/opos6uldev.h | 219 +++++++++++++++++ 13 files changed, 1396 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/mx6/opos6ul.c create mode 100644 arch/arm/dts/imx6ul-opos6ul.dtsi create mode 100644 arch/arm/dts/imx6ul-opos6uldev.dts create mode 100644 arch/arm/include/asm/arch-mx6/opos6ul.h create mode 100644 board/armadeus/opos6uldev/Kconfig create mode 100644 board/armadeus/opos6uldev/MAINTAINERS create mode 100644 board/armadeus/opos6uldev/Makefile create mode 100644 board/armadeus/opos6uldev/board.c create mode 100644 configs/opos6uldev_defconfig create mode 100644 include/configs/opos6uldev.h
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 19cc1f6..f31f612 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -42,6 +42,16 @@ config MX6UL_LITESOM select DM_THERMAL select SUPPORT_SPL
+config MX6UL_OPOS6UL + bool + select MX6UL + select BOARD_LATE_INIT + select DM + select DM_GPIO + select DM_MMC + select DM_THERMAL + select SUPPORT_SPL + config MX6ULL bool select MX6UL @@ -248,6 +258,10 @@ config TARGET_MX6ULL_14X14_EVK config TARGET_NITROGEN6X bool "nitrogen6x"
+config TARGET_OPOS6ULDEV + bool "Armadeus OPOS6ULDev board" + select MX6UL_OPOS6UL + config TARGET_OT1200 bool "Bachmann OT1200" select SUPPORT_SPL @@ -346,6 +360,7 @@ config SYS_SOC source "board/ge/bx50v3/Kconfig" source "board/advantech/dms-ba16/Kconfig" source "board/aristainetos/Kconfig" +source "board/armadeus/opos6uldev/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/barco/platinum/Kconfig" source "board/barco/titanium/Kconfig" diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile index 024f703..c183eb4 100644 --- a/arch/arm/cpu/armv7/mx6/Makefile +++ b/arch/arm/cpu/armv7/mx6/Makefile @@ -11,3 +11,4 @@ obj-y := soc.o clock.o obj-$(CONFIG_SPL_BUILD) += ddr.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_MX6UL_LITESOM) += litesom.o +obj-$(CONFIG_MX6UL_OPOS6UL) += opos6ul.o diff --git a/arch/arm/cpu/armv7/mx6/opos6ul.c b/arch/arm/cpu/armv7/mx6/opos6ul.c new file mode 100644 index 0000000..ea2f0ec --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/opos6ul.c @@ -0,0 +1,302 @@ +/* + * Copyright (C) 2017 Armadeus Systems + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/mx6ul_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <common.h> +#include <environment.h> +#include <fsl_esdhc.h> +#include <mmc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_FEC_MXC +#include <miiphy.h> + +#define MDIO_PAD_CTRL ( \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm \ +) + +#define ENET_PAD_CTRL_PU ( \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm \ +) + +#define ENET_PAD_CTRL_PD ( \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm \ +) + +#define ENET_CLK_PAD_CTRL ( \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \ +) + +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), + /* PHY Int */ + MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(ENET_PAD_CTRL_PU), + /* PHY Reset */ + MX6_PAD_NAND_DATA00__GPIO4_IO02 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), +}; + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct gpio_desc rst; + int ret; + + /* Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17] */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + + ret = dm_gpio_lookup_name("GPIO4_2", &rst); + if (ret) { + printf("Cannot get GPIO4_2\n"); + return ret; + } + + ret = dm_gpio_request(&rst, "phy-rst"); + if (ret) { + printf("Cannot request GPIO4_2\n"); + return ret; + } + + dm_gpio_set_dir_flags(&rst, GPIOD_IS_OUT); + dm_gpio_set_value(&rst, 0); + udelay(1000); + dm_gpio_set_value(&rst, 1); + + return fecmxc_initialize(bis); +} +#endif /* CONFIG_FEC_MXC */ + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int __weak opos6ul_board_late_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr2); + + /* In bootstrap don't use the env vars */ + if (((reg & 0x3000000) >> 24) == 0x1) { + set_default_env(NULL); + setenv("preboot", ""); + } + + return opos6ul_board_late_init(); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + return cfg->esdhc_base == USDHC1_BASE_ADDR; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/opos6ul.h> +#include <libfdt.h> +#include <spl.h> + +#define USDHC_PAD_CTRL ( \ + PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST \ +) + +struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 8}, +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000008, + .dram_sdqs0 = 0x00000038, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00070007, + .p0_mpdgctrl0 = 0x41490145, + .p0_mprddlctl = 0x40404546, + .p0_mpwrdlctl = 0x4040524D, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 20, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 800, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1500, + .trcmin = 5250, + .trasmin = 3750, +}; + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); +} + +static void spl_dram_init(void) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[4]; + struct fuse_bank4_regs *fuse = + (struct fuse_bank4_regs *)bank->fuse_regs; + int reg = readl(&fuse->gp1); + + /* 512MB of RAM */ + if (reg & 0x1) { + mem_ddr.density = 4; + mem_ddr.rowaddr = 15; + mem_ddr.trcd = 1375; + mem_ddr.trcmin = 4875; + mem_ddr.trasmin = 3500; + } + + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + opos6ul_setup_uart_debug(); + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index eb68c20..b4e7f44 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -316,7 +316,8 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6q-icore.dtb \ imx6q-icore-rqs.dtb \ imx6sx-sabreauto.dtb \ - imx6ul-geam-kit.dtb + imx6ul-geam-kit.dtb \ + imx6ul-opos6uldev.dtb
dtb-$(CONFIG_MX7) += imx7-colibri.dtb
diff --git a/arch/arm/dts/imx6ul-opos6ul.dtsi b/arch/arm/dts/imx6ul-opos6ul.dtsi new file mode 100644 index 0000000..51095df --- /dev/null +++ b/arch/arm/dts/imx6ul-opos6ul.dtsi @@ -0,0 +1,192 @@ +/* + * Copyright 2017 Armadeus Systems support@armadeus.com + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6ul.dtsi" + +/ { + memory { + reg = <0x80000000 0>; /* will be filled by U-Boot */ + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-reset-duration = <1>; + phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + phy-handle = <ðphy1>; + phy-supply = <®_3v3>; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupt-parent = <&gpio4>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + }; + }; +}; + +/* Bluetooth */ +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + uart-has-rtscts; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +/* WiFi */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc3_pwrseq>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio2>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + /* INT# */ + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0 + /* RST# */ + MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0 + /* BT_REG_ON */ + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0 + MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0 + MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0 + MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0 + MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0 + MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0 + /* WL_REG_ON */ + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0 + /* WL_IRQ */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6ul-opos6uldev.dts b/arch/arm/dts/imx6ul-opos6uldev.dts new file mode 100644 index 0000000..0e59ee5 --- /dev/null +++ b/arch/arm/dts/imx6ul-opos6uldev.dts @@ -0,0 +1,412 @@ +/* + * Copyright 2017 Armadeus Systems support@armadeus.com + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6ul-opos6ul.dtsi" + +/ { + model = "Armadeus Systems OPOS6UL SoM on OPOS6ULDev board"; + compatible = "armadeus,opos6uldev", "armadeus,opos6ul", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 191000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_5v>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + user-button { + label = "User button"; + gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + linux,code = <BTN_MISC>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + user-led { + label = "User"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + onewire { + compatible = "w1-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_w1>; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg1_vbus: regulator-usbotg1vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg1vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbotg2_vbus: regulator-usbotg2vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg2vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_vbus>; + gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc1 { + vref-supply = <®_3v3>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_5v>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_5v>; + status = "okay"; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <5000000>; + }; + + spidev1: spi@1 { + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <5000000>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock_frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock_frequency = <400000>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + display = <&display0>; + lcd-supply = <®_3v3>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <18>; + + display-timings { + timing0: timing0 { + clock-frequency = <33000033>; + hactive = <800>; + vactive = <480>; + hback-porch = <96>; + hfront-porch = <96>; + vback-porch = <20>; + vfront-porch = <21>; + hsync-len = <64>; + vsync-len = <4>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "disabled"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xffff>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_id>; + vbus-supply = <®_usbotg1_vbus>; + dr_mode = "otg"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbotg2_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpios>; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0 + MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0 + MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0 + MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0 + MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 + >; + }; + + pinctrl_gpios: gpiosgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0 + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0 + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0 + MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0 + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0 + MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + >; + }; + + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1 + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0 + >; + }; + + pinctrl_usbotg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0 + >; + }; + + pinctrl_usbotg2_vbus: usbotg2vbusgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 + >; + }; + + pinctrl_w1: w1grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0 + >; + }; +}; diff --git a/arch/arm/include/asm/arch-mx6/opos6ul.h b/arch/arm/include/asm/arch-mx6/opos6ul.h new file mode 100644 index 0000000..b536385 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/opos6ul.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2017 Armadeus Systems + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_ARM_MX6UL_OPOS6UL_H__ +#define __ARCH_ARM_MX6UL_OPOS6UL_H__ + +int opos6ul_board_late_init(void); + +#ifdef CONFIG_SPL_BUILD +void opos6ul_setup_uart_debug(void); +#endif + +#endif diff --git a/board/armadeus/opos6uldev/Kconfig b/board/armadeus/opos6uldev/Kconfig new file mode 100644 index 0000000..beca37d --- /dev/null +++ b/board/armadeus/opos6uldev/Kconfig @@ -0,0 +1,15 @@ +if TARGET_OPOS6ULDEV + +config SYS_BOARD + default "opos6uldev" + +config SYS_VENDOR + default "armadeus" + +config SYS_CONFIG_NAME + default "opos6uldev" + +config IMX_CONFIG + default "arch/arm/imx-common/spl_sd.cfg" + +endif diff --git a/board/armadeus/opos6uldev/MAINTAINERS b/board/armadeus/opos6uldev/MAINTAINERS new file mode 100644 index 0000000..e46c669 --- /dev/null +++ b/board/armadeus/opos6uldev/MAINTAINERS @@ -0,0 +1,6 @@ +OPOS6ULDev BOARD +M: Sébastien Szymanski sebastien.szymanski@armadeus.com +S: Maintained +F: board/armadeus/opos6uldev/ +F: include/configs/opos6uldev.h +F: configs/opos6uldev_defconfig diff --git a/board/armadeus/opos6uldev/Makefile b/board/armadeus/opos6uldev/Makefile new file mode 100644 index 0000000..fd14fd7 --- /dev/null +++ b/board/armadeus/opos6uldev/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2017 Armadeus Systems +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/armadeus/opos6uldev/board.c b/board/armadeus/opos6uldev/board.c new file mode 100644 index 0000000..500d0bd --- /dev/null +++ b/board/armadeus/opos6uldev/board.c @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2017 Armadeus Systems + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/opos6ul.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_VIDEO_MXS +#define LCD_PAD_CTRL ( \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm \ +) + +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +int setup_lcd(void) +{ + struct gpio_desc backlight; + int ret; + + enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Set Brightness to high */ + ret = dm_gpio_lookup_name("GPIO4_10", &backlight); + if (ret) { + printf("Cannot get GPIO4_10\n"); + return ret; + } + + ret = dm_gpio_request(&backlight, "backlight"); + if (ret) { + printf("Cannot request GPIO4_10\n"); + return ret; + } + + dm_gpio_set_dir_flags(&backlight, GPIOD_IS_OUT); + dm_gpio_set_value(&backlight, 1); + + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif + +int opos6ul_board_late_init(void) +{ +#ifdef CONFIG_VIDEO_MXS + setup_lcd(); +#endif + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#define UART_PAD_CTRL ( \ + PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \ +) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +void opos6ul_setup_uart_debug(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig new file mode 100644 index 0000000..5c3a3f6 --- /dev/null +++ b/configs/opos6uldev_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_OPOS6ULDEV=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_VIDEO=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-opos6uldev" +CONFIG_BOOTDELAY=5 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_DEFAULT_FDT_FILE="imx6ul-opos6uldev.dtb" +CONFIG_VERSION_VARIABLE=y +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="BIOS> " +CONFIG_CMD_CONFIG=y +CONFIG_CMD_LICENSE=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +# CONFIG_BLK is not set +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_PWRSEQ=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Armadeus Systems" +CONFIG_G_DNL_VENDOR_NUM=0x0525 +CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_OF_LIBFDT_OVERLAY=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h new file mode 100644 index 0000000..e5ab067 --- /dev/null +++ b/include/configs/opos6uldev.h @@ -0,0 +1,219 @@ +/* + * Copyright (C) 2017 Armadeus Systems + * + * Configuration settings for the OPOS6ULDev board + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OPOS6ULDEV_CONFIG_H +#define __OPOS6ULDEV_CONFIG_H + +#include "mx6_common.h" + +#ifdef CONFIG_SPL +#include "imx6_spl.h" + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_GPIO +#undef CONFIG_DM_MMC + +#define CONFIG_MXC_UART_BASE UART1_BASE +#endif +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 << 20) + +/* Miscellaneous configurable options */ +#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* MMC */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SUPPORT_EMMC_BOOT + +/* USB */ +#ifdef CONFIG_USB_EHCI_MX6 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#endif + +/* Ethernet */ +#ifdef CONFIG_FEC_MXC +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_MII +#endif + +/* LCD */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_SPLASH_SOURCE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_MXS +#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR +#endif + +/* Environment is stored in the eMMC boot partition */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 1 +#define CONFIG_ENV_SIZE (10 * 1024) +#define CONFIG_ENV_OFFSET (1024 * 1024) /* 1 MB */ +#define CONFIG_ENV_OFFSET_REDUND (1536 * 1024) /* 512KB from CONFIG_ENV_OFFSET */ + +#define CONFIG_ENV_VERSION 100 +#define CONFIG_BOARD_NAME opos6ul +#define ACFG_CONSOLE_DEV ttymxc0 +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" +#define CONFIG_BOOTARGS "console=" __stringify(ACFG_CONSOLE_DEV) "," __stringify(CONFIG_BAUDRATE) +#define CONFIG_PREBOOT "run check_env" +#define CONFIG_BOOTCOMMAND "run emmcboot" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ + "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ + "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ + "fdt_addr=0x88000000\0" \ + "fdt_high=0xffffffff\0" \ + "fdt_name=" __stringify(CONFIG_BOARD_NAME) "dev\0" \ + "initrd_high=0xffffffff\0" \ + "ip_dyn=yes\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "kernelimg=" __stringify(CONFIG_BOARD_NAME) "-linux.bin\0" \ + "videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0\0" \ + "check_env=if test -n ${flash_env_version}; " \ + "then env default env_version; " \ + "else env set flash_env_version ${env_version}; env save; " \ + "fi; " \ + "if itest ${flash_env_version} != ${env_version}; then " \ + "echo "*** Warning - Environment version" \ + " change suggests: run flash_reset_env; reset"; " \ + "env default flash_reset_env; " \ + "else exit; fi; \0" \ + "flash_reset_env=env default -f -a && saveenv && " \ + "echo Environment variables erased!\0" \ + "download_uboot_spl=tftpboot ${loadaddr} ${board_name}-u-boot.spl\0" \ + "flash_uboot_spl=" \ + "if mmc dev 0 1; then " \ + "setexpr sz ${filesize} / 0x200; " \ + "setexpr sz ${sz} + 1; " \ + "if mmc write ${loadaddr} 0x2 ${sz}; then " \ + "echo Flashing of U-boot SPL succeed; " \ + "else echo Flashing of U-boot SPL failed; " \ + "fi; " \ + "fi;\0" \ + "download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img\0" \ + "flash_uboot_img=" \ + "if mmc dev 0 1; then " \ + "setexpr sz ${filesize} / 0x200; " \ + "setexpr sz ${sz} + 1; " \ + "if mmc write ${loadaddr} 0x8a ${sz}; then " \ + "echo Flashing of U-boot image succeed; " \ + "else echo Flashing of U-boot image failed; " \ + "fi; " \ + "fi;\0" \ + "update_uboot=run download_uboot_spl flash_uboot_spl " \ + "download_uboot_img flash_uboot_img\0" \ + "download_kernel=tftpboot ${loadaddr} ${kernelimg}\0" \ + "flash_kernel=" \ + "if ext4write mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} ${filesize}; then " \ + "echo kernel update succeed; " \ + "else echo kernel update failed; " \ + "fi;\0" \ + "update_kernel=run download_kernel flash_kernel\0" \ + "download_dtb=tftpboot ${fdt_addr} imx6ul-${fdt_name}.dtb\0" \ + "flash_dtb=" \ + "if ext4write mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb ${filesize}; then " \ + "echo dtb update succeed; " \ + "else echo dtb update in failed; " \ + "fi;\0" \ + "update_dtb=run download_dtb flash_dtb\0" \ + "download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ext4\0" \ + "flash_rootfs=" \ + "if mmc dev 0 0; then " \ + "setexpr nbblocks ${filesize} / 0x200; " \ + "setexpr nbblocks ${nbblocks} + 1; " \ + "if mmc write ${loadaddr} 0x40800 ${nbblocks}; then " \ + "echo Flashing of rootfs image succeed; " \ + "else echo Flashing of rootfs image failed; " \ + "fi; " \ + "fi;\0" \ + "update_rootfs=run download_rootfs flash_rootfs\0" \ + "flash_failsafe=" \ + "if mmc dev 0 0; then " \ + "setexpr nbblocks ${filesize} / 0x200; " \ + "setexpr nbblocks ${nbblocks} + 1; " \ + "if mmc write ${loadaddr} 0x800 ${nbblocks}; then " \ + "echo Flashing of rootfs image in failsafe partition succeed; " \ + "else echo Flashing of rootfs image in failsafe partition failed; " \ + "fi; " \ + "fi;\0" \ + "update_failsafe=run download_rootfs flash_failsafe\0" \ + "download_userdata=tftpboot ${loadaddr} ${board_name}-user_data.ext4\0" \ + "flash_userdata=" \ + "if mmc dev 0 0; then " \ + "setexpr nbblocks ${filesize} / 0x200; " \ + "setexpr nbblocks ${nbblocks} + 1; " \ + "if mmc write ${loadaddr} 0 ${nbblocks}; then " \ + "echo Flashing of user_data image succeed; " \ + "else echo Flashing of user_data image failed; " \ + "fi; " \ + "fi;\0" \ + "update_userdata=run download_userdata flash_userdata; mmc rescan\0" \ + "erase_userdata=" \ + "if mmc dev 0 0; then " \ + "echo Erasing eMMC User Data partition, no way out...; " \ + "mw ${loadaddr} 0 0x200000; " \ + "mmc write ${loadaddr} 0 0x1000; " \ + "mmc write ${loadaddr} 0x800 0x1000; " \ + "mmc write ${loadaddr} 0x40800 0x1000; " \ + "mmc write ${loadaddr} 0x440800 0x1000; " \ + "fi;" \ + "mmc rescan\0" \ + "update_all=run update_rootfs update_uboot\0" \ + "initargs=setenv bootargs console=${consoledev},${baudrate} ${extrabootargs}\0" \ + "addipargs=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ + "addmmcargs=setenv bootargs ${bootargs} root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "emmcboot=run initargs; run addmmcargs; " \ + "load mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} && " \ + "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb && " \ + "bootz ${loadaddr} - ${fdt_addr};\0" \ + "emmcsafeboot=setenv mmcpart 1; setenv mmcroot /dev/mmcblk0p1 ro; run emmcboot;\0" \ + "addnfsargs=setenv bootargs ${bootargs} root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "nfsboot=run initargs; run addnfsargs addipargs; " \ + "nfs ${loadaddr} ${serverip}:${rootpath}/boot/${kernelimg} && " \ + "nfs ${fdt_addr} ${serverip}:${rootpath}/boot/imx6ul-${fdt_name}.dtb && " \ + "bootz ${loadaddr} - ${fdt_addr};\0" + +#endif /* __OPOS6ULDEV_CONFIG_H */