Hi Xiang,
On Fri, Feb 03, 2023 at 03:24:37PM +0100, David Abdurachmanov wrote:
On Mon, Jan 3, 2022 at 1:13 PM Leo Liang ycliang@andestech.com wrote:
On Thu, Dec 30, 2021 at 01:55:15AM +0800, Xiang W wrote:
在 2021-12-29星期三的 17:23 +0800，Leo Liang写道：
Hi Xiang, On Wed, Dec 22, 2021 at 07:32:53AM +0800, Xiang W wrote:
Various specifications of riscv allow the number of hart to be greater than 32. The limit of 32 is determined by gd->arch.available_harts. We can eliminate this limitation through bitmaps. Currently, the number of hart is limited to 4095, and 4095 is the limit of the RISC-V Advanced Core Local Interruptor Specification.
Test on sifive unmatched.
Signed-off-by: Xiang W wxjstz@126.com
Changes since v1:
- When NR_CPUS is very large, the value of GD_AVAILABLE_HARTS will overflow the immediate range of ld/lw. This patch fixes this problem
arch/riscv/Kconfig | 4 ++-- arch/riscv/cpu/start.S | 21 ++++++++++++++++----- arch/riscv/include/asm/global_data.h | 4 +++- arch/riscv/lib/smp.c | 2 +- 4 files changed, 22 insertions(+), 9 deletions(-)
I noticed that this has never landed in U-Boot. Was this forgotten or dropped for some reason (couldn't find anything)?
The current limit on the Linux kernel side is 512. The default on 64-bit (riscv64) is 64.
david
The patch seems to cause some CI error (timeout on QEMU). (https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/15076) Could you take a look at it if you have time?
Best regards, Leo