The sequence erroneously launched the DDR controller initialization before the pad muxing was done, causing DRAM size computation to hang.
Configuring the pads first then launching DDR controller initialization prevents the DRAM hanging.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr --- board/phytec/pcm052/pcm052.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index e75ff4fc3a..54a4e4f9c3 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -258,8 +258,7 @@ int dram_init(void) .wldqsen = 25, };
- ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, - pcm052_phy_settings, 1, 2); + const int row_diff = 2;
#elif defined(CONFIG_TARGET_BK4R1)
@@ -314,8 +313,7 @@ int dram_init(void) .wldqsen = 25, };
- ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, - pcm052_phy_settings, 1, 1); + const int row_diff = 1;
#else /* Unknown PCM052 variant */
@@ -325,6 +323,9 @@ int dram_init(void)
imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads));
+ ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, + pcm052_phy_settings, 1, row_diff); + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;