22 Aug
2015
22 Aug
'15
6:19 a.m.
On 15 August 2015 at 14:37, Simon Glass sjg@chromium.org wrote:
From: Bin Meng bmeng.cn@gmail.com
Intel FSP has the capability to walk through the microcode blocks which are passed as the TempRamInit() parameter from U-Boot and finds the most appropriate microcode which is suitable for the cpu on which it is running. Now we've seen several steppings for Intel BayTrail series processors, adding those microcodes to the Intel BayleyBay and MinnowMax board device tree files.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Signed-off-by: Simon Glass sjg@chromium.org
Changes in v2:
- Adjust to use separate nodes for each microcode block
arch/x86/dts/bayleybay.dts | 6 ++++++ arch/x86/dts/minnowmax.dts | 3 +++ 2 files changed, 9 insertions(+)
Applied to u-boot-x86, thanks!