From: u-boot-users-admin@lists.sourceforge.net [mailto:u-boot-users-admin@lists.sourceforge.net] On Behalf Of Thomas Schäfer Sent: Tuesday, February 01, 2005 11:10
- The solution provided in common/soft_i2c.c sets the SDA
line to 1 and issues 9 cycles on the SCL line. Is this an undefined I2C pattern causing a reset on the I2C bus (which is not specified in the I2C specification)? Why is it not sufficient to issue a simple Start/Stop sequence on the bus?
This has the effect of making sure that if a EEPROM (or other device) was in the middle of something when a reset occurred, it will get enough clocks to cycle through its state-machine to a point where it can detect a stop or abort. (24LC64 are notorious for this) This is only possible to do using the soft i2c. If you are using a hardware I2C, you are SOL if the external device is in the middle of a data-transfer when a reset occurs, because it WILL hang the I2C bus. Only way to reset the I2c device is to use the method soft_i2c uses, or power cycle the device.
And yes... I have seen this problem, on a PCI card with CPU on it that got reset by the host just as it was reading the onboard EEPROM. Locked the card up solid. Only way to recover was to turn the power off.