On the RK3399, SPI3 is special (it's configured via PMUGRF). The implementation of the clock-setup for SPI3 was never supported (and the comments reflected this), but the implementation did not correctly handle this.
This fixes the code to match the comments above it and returns an error when trying to configure SPI3.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com ---
drivers/clk/rockchip/clk_rk3399.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 53d2a3f..d0f52c1 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -637,10 +637,10 @@ static const struct spi_clkreg spi_clkregs[] = { [2] = { .reg = 60, .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT, .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, }, - [3] = { .reg = 60, + [4] = { .reg = 60, .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT, .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, }, - [4] = { .reg = 58, + [5] = { .reg = 58, .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT, .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, }; @@ -656,10 +656,15 @@ static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) u32 div, val;
switch (clk_id) { - case SCLK_SPI0 ... SCLK_SPI5: + case SCLK_SPI0: + case SCLK_SPI1: + case SCLK_SPI2: + case SCLK_SPI4: + case SCLK_SPI5: spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; break;
+ case SLCK_SPI3: default: error("%s: SPI clk-id %ld not supported\n", __func__, clk_id); return -EINVAL; @@ -680,10 +685,15 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) assert(src_clk_div < 127);
switch (clk_id) { - case SCLK_SPI1 ... SCLK_SPI5: + case SCLK_SPI0: + case SCLK_SPI1: + case SCLK_SPI2: + case SCLK_SPI4: + case SCLK_SPI5: spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; break;
+ case SLCK_SPI3: default: error("%s: SPI clk-id %ld not supported\n", __func__, clk_id); return -EINVAL;