From: Xu Ziyuan xzy.xu@rock-chips.com
The total FIFO size of dwc2 on Rockchip SoCs is shorter than the existen, so re-define them to fit Rockchip SoCs.
Signed-off-by: Ziyuan Xu xzy.xu@rock-chips.com
---
Changes in v3: None Changes in v2: - Update detailed commit message - Modify the macro's values
drivers/usb/gadget/dwc2_udc_otg_regs.h | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h index 78ec90e..6004a4b 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_regs.h +++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h @@ -130,9 +130,15 @@ struct dwc2_usbotg_reg { #define HIGH_SPEED_CONTROL_PKT_SIZE 64 #define HIGH_SPEED_BULK_PKT_SIZE 512
+#ifdef CONFIG_ARCH_ROCKCHIP +#define RX_FIFO_SIZE (512*4) +#define NPTX_FIFO_SIZE (16*4) +#define PTX_FIFO_SIZE (128*4) +#else #define RX_FIFO_SIZE (1024*4) #define NPTX_FIFO_SIZE (1024*4) #define PTX_FIFO_SIZE (1536*1) +#endif
#define DEPCTL_TXFNUM_0 (0x0<<22) #define DEPCTL_TXFNUM_1 (0x1<<22)