Add header file support of amic multicore interrupt controller.
Signed-off-by: Macpaul Lin macpaul@andestech.com --- include/andestech/amic.h | 195 ++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 195 insertions(+), 0 deletions(-) create mode 100644 include/andestech/amic.h
diff --git a/include/andestech/amic.h b/include/andestech/amic.h new file mode 100644 index 0000000..52d95ca --- /dev/null +++ b/include/andestech/amic.h @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2012 Andes Technology Corp + * Macpaul Lin macpaul@andestech.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Andes Multi-Core Interrupt Controller + */ +#ifndef __ANDES_AMIC_H +#define __ANDES_AMIC_H + +#ifndef __ASSEMBLY__ + +struct amic { + unsigned int intconfig; /* 0x00 - Hardware Configuration */ + unsigned int cpudc; /* 0x04 - CPU owner DC reg */ + unsigned int cpuid1; /* 0x08 - CPU owner ID reg 1 */ + unsigned int cpuid2; /* 0x0c - CPU owner ID reg 2 */ + unsigned int rsvd0[4]; /* 0x10-0x1c - Reserved */ + unsigned int intrigmode; /* 0x20 - Interrupt Trigger Mode */ + unsigned int intriglevel; /* 0x24 - Interrupt Trigger Level */ + unsigned int intsrc; /* 0x28 - Interrupt Source reg */ + unsigned int rsvd1[5]; /* 0x2c-0x3c - Reserved */ + unsigned int ipitrg; /* 0x40 - IPI trigger reg */ + unsigned int ipista; /* 0x44 - IPI status/clear reg */ + unsigned int ipipl; /* 0x48 - IPI priority level reg */ + unsigned int ipigsta; /* 0x4c - IPI global status/clear reg */ + unsigned int ipigpt; /* 0x50 - IPI global priority reg */ + unsigned int rsvd2[11]; /* 0x54-0x7c - Reserved */ + unsigned int inten; /* 0x80 - Interrupt enable reg */ + unsigned int intgsta; /* 0x84 - Interrupt status/clear reg */ + unsigned int inthw0sta; /* 0x88 - IVIC HW0 int status/clear */ + unsigned int inthw1sta; /* 0x8c - IVIC HW1 int status/clear */ + unsigned int inthw2sta; /* 0x90 - IVIC HW2 int status/clear */ + unsigned int inthw3sta; /* 0x94 - IVIC HW3 int status/clear */ + unsigned int inthw4sta; /* 0x98 - IVIC HW4 int status/clear */ + unsigned int inthw5sta; /* 0x9c - IVIC HW5 int status/clear */ + unsigned int iplcr0; /* 0xa0 - Int priority level0 0-7) */ + unsigned int iplcr1; /* 0xa4 - Int priority level1 8-15 */ + unsigned int iplcr2; /* 0xa8 - Int priority level2 16-23 */ + unsigned int iplcr3; /* 0xac - Int priority level3 24-31 */ +}; +#endif /* __ASSEMBLY__ */ + +/* + * 0x00 - Configuration Register (ro) + */ +#define ANDES_AMIC_CPU_CNT(x) (((x) & 0x7) > 0) +#define ANDES_AMIC_PLVL (1 << 4) +#define ANDES_AMIC_IPI32 (1 << 5) +#define ANDES_AMIC_EM0 (1 << 8) +#define ANDES_AMIC_EM1 (1 << 9) +#define ANDES_AMIC_EM2 (1 << 10) +#define ANDES_AMIC_EM3 (1 << 11) +#define ANDES_AMIC_VER(x) (((x) & 0xffff0000) > 16) + +/* + * 0x04 - CPU owner DC register + */ +#define ANDES_AMIC_CPUDC(x) ((x) & 0xffffffff) + +/* + * 0x08 - CPU owner ID register 1 + */ +#define ANDES_AMIC_CPUID1(x) (((x) & 0x0000ffff) > 0) + +/* + * 0x0c - CPU owner ID register 2 + */ +#define ANDES_AMIC_CPUID2(x) (((x) & 0xffff0000) > 16) + +/* + * 0x20 - Interrupt Trigger Mode Register + * 0: level trigger, 1: edge trigger + */ +#define ANDES_AMIC_INTRIGMODE(x) (1 << (x)) + +/* + * 0x24 - Interrupt Trigger Level Register + * 0: Active-high/rising edge, 1: Active-low/falling edge + */ +#define ANDES_AMIC_INTRIGLEVEL(x) (1 << (x)) + +/* + * 0x28 - Interrupt Source Register + */ +#define ANDES_AMIC_INTRSRC(x) (1 << (x)) + +/* + * 0x040 - IPI Trigger Register + */ +#define ANDES_AMIC_IPITRG_CX0 (1 << 0) +#define ANDES_AMIC_IPITRG_CX1 (1 << 1) +#define ANDES_AMIC_IPITRG_CX2 (1 << 2) +#define ANDES_AMIC_IPITRG_CX3 (1 << 3) + +/* + * 0x044 - IPI Status/Clear register + */ +#define ANDES_AMIC_IPISTA_CX0 (1 << 0) +#define ANDES_AMIC_IPISTA_CX1 (1 << 1) +#define ANDES_AMIC_IPISTA_CX2 (1 << 2) +#define ANDES_AMIC_IPISTA_CX3 (1 << 3) + +/* + * 0x48 - IPI Priority Level register + */ +#define ANDES_AMIC_IPIPL(x) (((x) & 0x7) << 0) + +/* + * 0x04c - IPI Global Status/Clear register + * Read: indicate all Inter-Processor Interrupt (IPI) status. + * The name of each bit is "C<source><target>" + * and the meaning is "CPU<source> call CPU<target>" + * Write : Any CPU can write 1 to clear any one bit of ipigsta + * to make that the "CPU<source> call CPU <target>" event + * have been serviced. + */ +#define ANDES_AMIC_IPIGSTA_C00 (1 << 0) +#define ANDES_AMIC_IPIGSTA_C10 (1 << 1) +#define ANDES_AMIC_IPIGSTA_C20 (1 << 2) +#define ANDES_AMIC_IPIGSTA_C30 (1 << 3) +#define ANDES_AMIC_IPIGSTA_C01 (1 << 4) +#define ANDES_AMIC_IPIGSTA_C11 (1 << 5) +#define ANDES_AMIC_IPIGSTA_C21 (1 << 6) +#define ANDES_AMIC_IPIGSTA_C31 (1 << 7) +#define ANDES_AMIC_IPIGSTA_C02 (1 << 8) +#define ANDES_AMIC_IPIGSTA_C12 (1 << 9) +#define ANDES_AMIC_IPIGSTA_C22 (1 << 10) +#define ANDES_AMIC_IPIGSTA_C32 (1 << 11) +#define ANDES_AMIC_IPIGSTA_C03 (1 << 12) +#define ANDES_AMIC_IPIGSTA_C13 (1 << 13) +#define ANDES_AMIC_IPIGSTA_C23 (1 << 14) +#define ANDES_AMIC_IPIGSTA_C33 (1 << 15) + +/* + * 0x050 - IPI Global Priority Register + */ +#define ANDES_AMIC_IPIGPT_C0PT(x) (((x) & 0x7) << 0) +#define ANDES_AMIC_IPIGPT_C1PT(x) (((x) & 0x7) << 4) +#define ANDES_AMIC_IPIGPT_C2PT(x) (((x) & 0x7) << 8) +#define ANDES_AMIC_IPIGPT_C3PT(x) (((x) & 0x7) << 12) + +/* + * 0x80 - Interrupt Enable Register + */ +#define ANDES_AMIC_INTEN(x) (1 << (x)) + +/* + * 0x84 - Interrupt Enable Register + */ +#define ANDES_AMIC_GSTA(x) (1 << (x)) + +/* + * 0x88-0x9c - IVIC HW0~HW5 Status Register + * Read: Shows the priority level corresponding HW0-5 status of + * the CPU ID owner interrupts after masking by the enable registers. + * A HIGH bit indicates that the appropriate interrupt request is + * active after masking. + * Write: A HIGH bit clears the corresponding bit in the intsrcreg which + * is edge trigger mode. A LOW bit has no effect. + */ +#define ANDES_AMIC_HWSTA(x) (1 << (x)) + +/* + * 0xA0-0xAC - Interrupt priority level configuration registers + * + * 0xA0: 0~7, 0xA4: 8~15, 0xA8: 16~23, 0xAC: 24~31 + * Each interrupt input can be configured the priority level from + * level 0(max.) to level 7(min.). + */ +#define ANDES_AMIC_IPLCR_HW0(x) (((x) & 0x7) << 0) +#define ANDES_AMIC_IPLCR_HW1(x) (((x) & 0x7) << 4) +#define ANDES_AMIC_IPLCR_HW2(x) (((x) & 0x7) << 8) +#define ANDES_AMIC_IPLCR_HW3(x) (((x) & 0x7) << 12) +#define ANDES_AMIC_IPLCR_HW4(x) (((x) & 0x7) << 16) +#define ANDES_AMIC_IPLCR_HW5(x) (((x) & 0x7) << 20) +#define ANDES_AMIC_IPLCR_HW6(x) (((x) & 0x7) << 24) +#define ANDES_AMIC_IPLCR_HW7(x) (((x) & 0x7) << 28) + +#endif /* __ANDES_PCU_H */