Update this uclass to support the needs of the Apollo Lake ITSS. It supports four operations.
Move the uclass into a separate directory so that sandbox can use it too. Add a new Kconfig to control it and enable this on x86.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v4: - Drop itss uclass in Makefile - Fix 'enabled' typo - apollolake -> Apollo Lake
Changes in v3: - Add two more operations to IRQ - Use the IRQ uclass instead of creating a new ITSS uclass
Changes in v2: None
arch/Kconfig | 1 + arch/x86/cpu/irq.c | 5 --- drivers/misc/Kconfig | 9 ++++ drivers/misc/Makefile | 1 + drivers/misc/irq-uclass.c | 53 +++++++++++++++++++++++ include/irq.h | 88 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 152 insertions(+), 5 deletions(-) create mode 100644 drivers/misc/irq-uclass.c create mode 100644 include/irq.h
diff --git a/arch/Kconfig b/arch/Kconfig index e1f1fcd275..6865e1f909 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -186,6 +186,7 @@ config X86 imply USB_HOST_ETHER imply PCH imply RTC_MC146818 + imply IRQ
# Thing to enable for when SPL/TPL are enabled: SPL imply SPL_DM diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 3adc155818..cb183496b7 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -370,8 +370,3 @@ U_BOOT_DRIVER(irq_router_drv) = { .probe = irq_router_probe, .priv_auto_alloc_size = sizeof(struct irq_router), }; - -UCLASS_DRIVER(irq) = { - .id = UCLASS_IRQ, - .name = "irq", -}; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 71643af9c2..f18aa8f7ba 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -203,6 +203,15 @@ config FSL_SEC_MON Security Monitor can be transitioned on any security failures, like software violations or hardware security violations.
+config IRQ + bool "Intel Interrupt controller" + depends on X86 || SANDBOX + help + This enables support for Intel interrupt controllers, including ITSS. + Some devices have extra features, such as Apollo Lake. The + device has its own uclass since there are several operations + involved. + config JZ4780_EFUSE bool "Ingenic JZ4780 eFUSE support" depends on ARCH_JZ47XX diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 44c9e3ef08..28313e4a65 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_FS_LOADER) += fs_loader.o obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o +obj-$(CONFIG_IRQ) += irq-uclass.o obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o obj-$(CONFIG_IMX8) += imx8/ diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c new file mode 100644 index 0000000000..d5182cf149 --- /dev/null +++ b/drivers/misc/irq-uclass.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com + */ + +#include <common.h> +#include <dm.h> +#include <irq.h> + +int irq_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num) +{ + const struct irq_ops *ops = irq_get_ops(dev); + + if (!ops->route_pmc_gpio_gpe) + return -ENOSYS; + + return ops->route_pmc_gpio_gpe(dev, pmc_gpe_num); +} + +int irq_set_polarity(struct udevice *dev, uint irq, bool active_low) +{ + const struct irq_ops *ops = irq_get_ops(dev); + + if (!ops->set_polarity) + return -ENOSYS; + + return ops->set_polarity(dev, irq, active_low); +} + +int irq_snapshot_polarities(struct udevice *dev) +{ + const struct irq_ops *ops = irq_get_ops(dev); + + if (!ops->snapshot_polarities) + return -ENOSYS; + + return ops->snapshot_polarities(dev); +} + +int irq_restore_polarities(struct udevice *dev) +{ + const struct irq_ops *ops = irq_get_ops(dev); + + if (!ops->restore_polarities) + return -ENOSYS; + + return ops->restore_polarities(dev); +} + +UCLASS_DRIVER(irq) = { + .id = UCLASS_IRQ, + .name = "irq", +}; diff --git a/include/irq.h b/include/irq.h new file mode 100644 index 0000000000..01ded64f16 --- /dev/null +++ b/include/irq.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * IRQ is a type of interrupt controller used on recent Intel SoC. + * + * Copyright 2019 Google LLC + */ + +#ifndef __irq_H +#define __irq_H + +/** + * struct irq_ops - Operations for the IRQ + */ +struct irq_ops { + /** + * route_pmc_gpio_gpe() - Get the GPIO for an event + * + * @dev: IRQ device + * @pmc_gpe_num: Event number to check + * @returns GPIO for the event, or -ENOENT if none + */ + int (*route_pmc_gpio_gpe)(struct udevice *dev, uint pmc_gpe_num); + + /** + * set_polarity() - Set the IRQ polarity + * + * @dev: IRQ device + * @irq: Interrupt number to set + * @active_low: true if active low, false for active high + * @return 0 if OK, -EINVAL if @irq is invalid + */ + int (*set_polarity)(struct udevice *dev, uint irq, bool active_low); + + /** + * snapshot_polarities() - record IRQ polarities for later restore + * + * @dev: IRQ device + * @return 0 + */ + int (*snapshot_polarities)(struct udevice *dev); + + /** + * restore_polarities() - restore IRQ polarities + * + * @dev: IRQ device + * @return 0 + */ + int (*restore_polarities)(struct udevice *dev); +}; + +#define irq_get_ops(dev) ((struct irq_ops *)(dev)->driver->ops) + +/** + * irq_route_pmc_gpio_gpe() - Get the GPIO for an event + * + * @dev: IRQ device + * @pmc_gpe_num: Event number to check + * @returns GPIO for the event, or -ENOENT if none + */ +int irq_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num); + +/** + * irq_set_polarity() - Set the IRQ polarity + * + * @dev: IRQ device + * @irq: Interrupt number to set + * @active_low: true if active low, false for active high + * @return 0 if OK, -EINVAL if @irq is invalid + */ +int irq_set_polarity(struct udevice *dev, uint irq, bool active_low); + +/** + * irq_snapshot_polarities() - record IRQ polarities for later restore + * + * @dev: IRQ device + * @return 0 + */ +int irq_snapshot_polarities(struct udevice *dev); + +/** + * irq_restore_polarities() - restore IRQ polarities + * + * @dev: IRQ device + * @return 0 + */ +int irq_restore_polarities(struct udevice *dev); + +#endif