Dear Drasko DRASKOVIC,
In message 5ec3d7930907130900l7e043b11lcf37a0d3e161f511@mail.gmail.com you wrote:
Well, that's easy - as the code has to interface with GCC generated code, you have to stick with GCC's register usage conventions.
I think we were refering here to ATPCS (ARM-THUMB Procedure Call Standard, i.e. ARM ABI), which tells that first 4 args of the calee are passed by the caller via r0-r3, and if calee takes more args, the rest is passed via stack. IMHO, GCC conventions has not much to do with this. I used r10 because there is small probability that it will be clobbered in start.S.
When I wrote "GCC's register usage conventions" I usually mean exactly that and not some completely different thing.
You also might want to read the README. Search for "On ARM, the following registers are used"...
"register volatile" makes sense only for the special case of global
or local register variables. Whether or not it is implemented in a specific version of GCC for a specific architecture is another story; please ask this on the GCC mailing list.
OK. But since it was implemented in U-Boot and for ARM, I thought that anybody who wrote this will be so kind to shread some light on this (I am guessing that that it has something to do with ISR, but in ISR we seem to
This has nothing to do with ISRs at all. What makes you think so?
preserve r8), and also on the membar two lines below, and spare me from subscribing to a huge volume gcc mailing lists for posting just one question. This rests for me one of the most obscure corners of U-Boot.
The GCC mailing list is where GCC experts can answer your questions. I'm not a GCC expert - just a happy user since version 1.35 or so...
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And please don't post HTML.
Best regards,
Wolfgang Denk