Re: [PATCH v2 13/13] rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash

18 May 2023

Hi Jonas,
On 2023/5/18 02:26, Jonas Karlman wrote:
...
Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 5 Model B.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
Reviewed-by: Kever Yang kever.yang@rock-chips.com

v2:

Add and use BROM_BOOTSOURCE_SPINOR_RK3588 enum value

Rebased to resolve conflicts

Collect r-b tag
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi      | 24 ++++++++++++++++++++
arch/arm/dts/rk3588s-u-boot.dtsi             | 20 ++++++++++++++++
arch/arm/include/asm/arch-rockchip/bootrom.h |  1 +
arch/arm/mach-rockchip/rk3588/rk3588.c       |  1 +
configs/rock5b-rk3588_defconfig              | 10 ++++++++
5 files changed, 56 insertions(+)

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index db342e6a9391..1cd8a57a6fa6 100644
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -11,6 +11,7 @@
  / {
   aliases {
   	mmc1 = &sdmmc;

spi0 = &sfc;

};
chosen {


@@ -54,6 +55,10 @@
   bootph-all;
  };
+&fspim2_pins {

bootph-all;

+};

&pcie2x1l2 {
 pinctrl-names = "default";
 pinctrl-0 = <&pcie2x1l2_pins &pcie_reset_h>;

@@ -123,6 +128,25 @@
   pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;
  };
+&sfc {

bootph-pre-ram;
u-boot,spl-sfc-no-dma;
pinctrl-names = "default";
pinctrl-0 = <&fspim2_pins>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";

flash@0 {
bootph-pre-ram;


compatible = "jedec,spi-nor";


reg = <0>;


spi-max-frequency = <24000000>;


spi-rx-bus-width = <4>;


spi-tx-bus-width = <1>;


};

+};

&uart2m0_xfer {
 bootph-all;
};

diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 2c4cad82b38f..64c309046587 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -165,6 +165,15 @@
   	};
   };

sfc: spi@fe2b0000 {
compatible = "rockchip,sfc";


reg = <0x0 0xfe2b0000 0x0 0x4000>;


interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;


clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;


clock-names = "clk_sfc", "hclk_sfc";


status = "disabled";


};
otp: nvmem@fecc0000 {
  compatible = "rockchip,rk3588-otp";
  reg = <0x0 0xfecc0000 0x0 0x400>;

@@ -241,3 +250,14 @@
  &ioc {
   bootph-pre-ram;
  };



+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+&binman {

simple-bin-spi {
mkimage {


	args = "-n", CONFIG_SYS_SOC, "-T", "rksd";


	offset = <0x8000>;


};


};

+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h
index 4276a0f6811a..7dab18fbc3fb 100644
--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -48,6 +48,7 @@ enum {
   BROM_BOOTSOURCE_SPINOR = 3,
   BROM_BOOTSOURCE_SPINAND = 4,
   BROM_BOOTSOURCE_SD = 5,

BROM_BOOTSOURCE_SPINOR_RK3588 = 6,

Why we need a new type of SPINOR_RK3588?
And this patch not able to apply due to conflict at rk3588s-u-boot.dtsi.
...
BROM_BOOTSOURCE_USB = 10,
   BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB
  };
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c
index 18e67b5ca9b2..b1f535fad505 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -41,6 +41,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
   [BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e0000",
   [BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b0000/flash@0",
   [BROM_BOOTSOURCE_SD] = "/mmc@fe2c0000",

[BROM_BOOTSOURCE_SPINOR_RK3588] = "/spi@fe2b0000/flash@0",

BROM_BOOTSOURCE_SPINOR is already there, why add BROM_BOOTSOURCE_SPINOR_RK3588 ?
Thanks,
- Kever
...
};
static struct mm_region rk3588_mem_map[] = {
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 5fe3a3542e11..9d0b55c01ac9 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -8,15 +8,20 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
  CONFIG_NR_DRAM_BANKS=2
  CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x2000
  CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
  CONFIG_ROCKCHIP_RK3588=y
  CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
  CONFIG_SPL_SERIAL=y
  CONFIG_SPL_STACK_R_ADDR=0x600000
  CONFIG_TARGET_ROCK5B_RK3588=y
  CONFIG_SPL_STACK=0x400000
  CONFIG_DEBUG_UART_BASE=0xFEB50000
  CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
  CONFIG_SYS_LOAD_ADDR=0xc00800
  CONFIG_PCI=y
  CONFIG_DEBUG_UART=y
@@ -36,6 +41,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
  # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
  # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
  CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
  CONFIG_SPL_ATF=y
  CONFIG_CMD_GPIO=y
  CONFIG_CMD_GPT=y
@@ -61,6 +68,8 @@ CONFIG_MMC_SDHCI=y
  CONFIG_MMC_SDHCI_SDMA=y
  # CONFIG_SPL_MMC_SDHCI_SDMA is not set
  CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_XTX=y
  CONFIG_ETH_DESIGNWARE=y
  CONFIG_GMAC_ROCKCHIP=y
  CONFIG_PCIE_DW_ROCKCHIP=y
@@ -73,6 +82,7 @@ CONFIG_SPL_RAM=y
  CONFIG_BAUDRATE=1500000
  CONFIG_DEBUG_UART_SHIFT=2
  CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
  CONFIG_SYSRESET=y
  CONFIG_USB=y
  CONFIG_USB_EHCI_HCD=y

    