On Wed, Aug 20, 2014 at 6:24 PM, Fabio Estevam festevam@gmail.com wrote:
From: Fabio Estevam fabio.estevam@freescale.com
Do not indicate an error when the buffer ready flag (FEC_TBD_READY) is set.
Without this change, mx6solox is not capable of doing TFTP transfers.
Succesfully tested on mx25, mx28, mx51, mx53, mx6q, mx6sl and mx6sx.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com
As you explicitly tested it in several SoC types it seems right however Marek has explicitly add this code in:
FEC: Rework the TX wait mechanism
The mechanism waiting for transmission to finish in fec_send() now relies on the E-bit being cleared in the TX buffer descriptor. In case of data cache being on, this means invalidation of data cache above this TX buffer descriptor on each test for the E-bit being cleared.
Apparently, there is another way to check if the transmission did complete. This is by checking the TDAR bit in the X_DES_ACTIVE register. Reading a register does not need any data cache invalidation, which is beneficial.
Rework the sequence that wait for completion of the transmission so that the TDAR bit is tested first and afterwards check the E-bit being clear. This cuts down the number of cache invalidation calls to one.
May Marek recall why this was need?