Hello everyone, recently I'm trying to port the newest version of u boot to my ipq4019 development board, and I found that the current serial driver for Qualcomm ipq40xx socs at u-boot-2022.01/drivers/serial/serial_msm.c is not compatible to ipq40xx despite they share the same compatible string in the device tree: u-boot-2022.01/drivers/serial/serial_msm.c: static const struct udevice_id msm_serial_ids[] = { { .compatible = "qcom,msm-uartdm-v1.4" }, { } };
u-boot-2022.01/arch/arm/dts/qcom-ipq4019.dtsi: blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; [...] }; I do have a confirmed working driver at hand, by comparing the code, I believe the reason behind this is the ipq40xx has a different register map than the current driver: Register map of my working diver at hand: struct ipq_serial_regs { unsigned int mr1; /* 0x00 - Operational Mode Register 1 */ unsigned int mr2; /* 0x04 - Operational Mode Register 2 */ unsigned int sr_csr; /* 0x08 - Status Register, Clock Selection Register */ unsigned char gap0[4]; /* 0x0C - gap */ unsigned int cr_misr; /* 0x10 - Command Register, Masked Interrupt Status Register */ unsigned int imr_isr; /* 0x14 - Interrupt Mask Register, Interrupt Status Register */ unsigned int ipr; /* 0x18 - Interrupt Programming Register */ unsigned int tfwr; /* 0x1C - Transmit FIFO Watermark Register */ unsigned int rfwr; /* 0x20 - Receive FIFO Watermark Register */ unsigned int hcr; /* 0x24 - Hunt Character Register */ unsigned char gap1[12]; /* 0x28 - gap */ unsigned int dmrx; /* 0x34 - RX transfer initialization */ unsigned int ncfrx_irda; /* 0x38 - Number of characters received since the end of last RX transfer, IRDA function Register */ unsigned int dmem; /* 0x3C - Data Mover Enable Register */ unsigned int ncftx; /* 0x40 - Number of characters for Transmission */ unsigned int badrr; /* 0x44 - RX FIFO Base Address */ unsigned char gap2[4]; /* 0x48 - gap */ unsigned int txfs; /* 0x4C - TX FIFO Status Register */ unsigned int rxfs; /* 0x50 - RX FIFO Status Register */ unsigned char gap3[28]; /* 0x54 - gap */ unsigned int rftf; /* 0x70 - UART Transmit and Receive FIFO Register */ };
Register definition bit at u-boot-2022.01/drivers/serial/serial_msm.c: #define UARTDM_MR1 0x00 #define UARTDM_MR2 0x04 #define UARTDM_DMRX 0x34 /* Max RX transfer length */ #define UARTDM_DMEN 0x3C /* DMA/data-packing mode */ #define UARTDM_NCF_TX 0x40 /* Number of chars to TX */ #define UARTDM_RXFS 0x50 /* RX channel status register */ #define UARTDM_ISR_TX_READY 0x80 /* TX FIFO empty */ #define UARTDM_CSR 0xA0 #define UARTDM_SR 0xA4 /* Status register */ #define UARTDM_CR 0xA8 /* Command register */ #define UARTDM_IMR 0xB0 /* Interrupt mask register */ #define UARTDM_ISR 0xB4 /* Interrupt status register */ #define UARTDM_TF 0x100 /* UART Transmit FIFO register */ #define UARTDM_RF 0x140 /* UART Receive FIFO register */
As you can see, for example: the working one's Transmit and Receive register definition is at an address of base + 0x70 while the current one's is at base + 0x100 and base + 0x140, so when the device is reading and sending things using current driver, they are doing it with wrong address and the serial won't work. I think this should be somehow fixed. Thanks.